CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 22

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

which is approximately 3 ppm. Care must be taken
in selecting a suitable clock source.
In MPEG-2 system environments the clock is actu-
ally recovered from the data stream. In these cases
the recovered clock can be 27 MHz 50 ppm or
±1350 Hz. It varies per television, but in many cas-
es given an MPEG-2 system clock of 27 MHz,
±1350 Hz, the resultant color subcarrier produced
will be outside of the television’s ability to com-
pensate and the chrominance information will not
be displayed (resulting in a black-and-white picture
only).
The CS4954/5 is designed to provide automatic
compensation for an excessively inaccurate
MPEG-2 system clock. Sub-carrier compensation
is enabled through the XTAL bit of the
CONTROL_2
CS4954/5 will utilize a common quartz color burst
crystal (3.579545 MHz ± 50 ppm for NTSC) at-
tached to the XTAL_IN and XTAL_OUT pins to
automatically compare and compensate the color
subcarrier synthesis process.
5.8.
The CS4954/5 is capable of NTSC Closed Caption
insertion on lines 21 and 284 independently.
Closed captioning is enabled for either one or both
lines via the CC_EN [1:0] Register bits and the
22
Address
0×00
0×01
0×04
0×05
0×10
0×12
0×13
0×14
0×11
Closed Caption Insertion
CONTROL_0
CONTROL_1
CONTROL_4
CONTROL_5
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
Register.
SC_AMP
Register
Table 4. Multi-standard Format Register Configurations
When
R.BT601
NTSC-M
1Ch
3Eh
F8h
E0h
ITU
01h
12h
07h
78h
43h
enabled
R.BT601
NTSC-J
1Ch
3Eh
F8h
E0h
ITU
01h
10h
07h
78h
43h
the
NTSC-M
RS170A
1Ch
3Eh
F8h
E0h
data to be inserted is also written into the four
Closed Caption Data registers. The CS4954/5,
when enabled, automatically generates the seven
cycles of clock run-in (32 times the line rate), start
bit insertion (001), and finally insertion of the two
data bytes per line. Data low at the video outputs
corresponds to 0 IRE and data high corresponds to
50 IRE.
There are two independent 8-bit registers per line
(CC_21_1 & CC_21_2 for line 21 and CC_284_1
& CC_284_2 for line 284). Interrupts are also pro-
vided to simplify the handshake between the driver
software and the device. Typically the host would
write all 4 bytes to be inserted into the registers and
then enable closed caption insertion and interrupts.
As the closed caption interrupts occur the host soft-
ware would respond by writing the next two bytes
to be inserted to the correct control registers and
then clear the interrupt and wait for the next field.
5.9.
It is possible in master mode to change the H-sync
and V-sync times based on register settings. Pro-
grammable H-sync and V-sync timings are helpful
in several digital video systems, where latencies of
the control signals are present. The user can then
program H-sync and V-sync timing according to
their system requirements. The default values are
244, and 264 for NTSC and PAL respectively.
21h
16h
07h
78h
43h
B,D,G,H,I
Programmable H-sync and V-sync
PAL-
41h
30h
07h
78h
15h
96h
15h
13h
54h
PAL-M
CDh
C7h
DFh
61h
12h
07h
78h
15h
43h
CS4954 CS4955
PAL-N
A1h
30h
07h
78h
15h
96h
15h
13h
54h
(Argent)
Comb.
PAL-N
8Ch
EDh
81h
30h
07h
78h
15h
28h
43h
DS278PP4