CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 15

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.2.
5.2.1. Slave Mode Input Interface
In Slave Mode, the CS4954/5 receives signals on
VSYNC and HSYNC as inputs. Slave Mode is the
default following RESET and is changed to Master
Mode via a control register bit (CONTROL_0 [4]).
The CS4954/5 is limited to ITU R.BT601 horizon-
tal and vertical input timing. All clocking in the
CS4954/5 is generated from the CLK pin. In Slave
Mode, the Sync Generator uses externally provided
horizontal and vertical sync signals to synchronize
the internal timing of the CS4954/5. Video data that
is sent to the CS4954/5 must be synchronized to the
horizontal and vertical sync signals. Figure 4 illus-
trates horizontal timing for ITU R.BT601 input in
Slave Mode. Note that the CS4954/5 expects to re-
ceive the first active pixel data on clock cycle 245
(NTSC) when CONTROL_2 Register (0x02) bit
DS278PP4
NTSC 27MHz Clock Count
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
PAL 27MHz Clock Count
Video Timing
HSYNC (output)
(SYNC_DLY=0)
(SYNC_DLY=1)
HSYNC (input)
CB (output)
V[7:0]
V[7:0]
V[7:0]
CLK
CLK
active pixel
• • •
• • •
Cb
1682
1702
Y
1682
1702
Y
#719
Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing
active pixel
active pixel
Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing
Cr
1683
1703
Y
Cr
1683
1703
#720
#720
active pixel
Cr
1684
1704
Y
1684
1704
Y
#720
1685
1705
Y
1685
1705
1686
1706
1686
1706
• • •
• • •
• • •
• • •
1716
1728
1716
1728
horizontal blanking
1
1
horizontal blanking
1
1
horizontal blanking
SYNC_DLY = 0. When SYNC_DLY = 1, it expects
the first active pixel data on clock cycle 246 (NTSC).
5.2.2. Master Mode Input Interface
The CS4954/5 defaults to Slave Mode following
RESET high but can be switched into Master Mode
via the MSTR bit in the CONTROL_0 Register
(0x00). In Master Mode, the CS4954/5 uses the
VSYNC, HSYNC and FIELD device pins as out-
puts to schedule the proper external delivery of dig-
ital video into the V [7:0] pins. Figure 5 illustrates
horizontal timing for the CCIR601 input in Master
Mode.
The timing of the HSYNC output is selectable in
the PROG_HS Registers (0x0D, 0x0E). HSYNC
can be delayed by one full line cycle. The timing of
the VSYNC output is also selectable in the
2
2
2
2
3
3
3
3
• • •
• • •
• • •
• • •
128
128
128
128
129
129
129
129
• • •
• • •
• • •
• • •
244
264
244
264
CS4954 CS4955
active pixel
active pixel
Cb
Cb
245
265
245
265
#1
#1
active pixel
Cb
Y
246
266
Y
246
266
#1
active pixel
active pixel
Cr
Y
Cr
247
267
247
267
#2
#2
active pixel
Cr
Y
248
268
Y
248
268
#2
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