CS4360-KS Cirrus Logic Inc, CS4360-KS Datasheet - Page 24

• Manufacturer Part Number: CS4360-KS
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4360-KS

• No. Of Pins: 28
• No. Of Bits: 24 Bit
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 28-SOIC

4.4.1
The operational mode pins, M2 and M1, selects the 44.1 kHz de-emphasis filter. Please see section 4.1
for the desired de-emphasis control.
4.4.2
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3
for the desired de-emphasis control.
4.5
4.5.1
1) Hold RST low until the power supply and configuration pins are stable, and the master and left/right
2) Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-
4.5.2
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
2) Bring RST high. The device will remain in a low power state with VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when
4.6
The CS4360 uses a novel technique to minimize the effects of output transients during power-up and pow-
er-down. This technology, when used with external DC-blocking capacitors in series with the audio out-
puts, minimizes the audio transients commonly produced by single-ended single-supply converters. It is
activated inside the DAC when the RST pin or PDN bit is enabled/disabled and requires no other external
control, aside from choosing the appropriate DC-blocking capacitors.
4.6.1
When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND.
Following a delay of approximately 1000 LRCK cycles, each output begins to ramp toward the quiescent
voltage. Approximately 10,000 LRCK cycles later, the outputs reach V
gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent
voltage, minimizing the power-up transient.
4.6.2
To prevent transients at power-down, the device must first enter its power-down state. When this occurs,
audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their
place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge.
Once this charge is dissipated, the power to the device may be turned off and the system is ready for the
next power-on.
24
clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control
port is reset to its default settings and VQ will remain low.
alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK
cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default
settings and VQ will remain low.
the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of pow-
er-up timing.
Recommended Power-up Sequence
Popguard
Stand-Alone Mode
Control Port Mode
Stand-Alone Mode
Control Port Mode
Power-up
Power-down
®
Transient Control
Q
and audio output begins. This
CS4360
DS517F2