CS4340-KS Cirrus Logic Inc, CS4340-KS Datasheet - Page 15

• Manufacturer Part Number: CS4340-KS
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4340-KS

• Resolution (bits): 24bit
• Data Interface: Serial
• No. Of Pins: 16
• Update Rate: 96kSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• No. Of Bits: 24 Bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS297PP3
DIF1 and DIF0
FILT+
VQ
REF_GND
AOUTR and AOUTL
AGND
VA
MUTEC
12 & 15 Analog Outputs ( Output ) - The full scale analog output level is specified in the Analog Charac-
6 & 7 Digital Interface Format (I nput ) - The required relationship between the Left/Right clock, serial
10
13
14
16
11
9
clock and serial data is defined by the Digital Interface Format and the options are detailed in
Figures 16-19
Positive Voltage Reference ( Output ) - Positive reference for internal sampling circuits. An
external capacitor is required from FILT+ to analog ground, as shown in Figure 4. The recom-
mended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz.
FILT+ is not intended to supply external current. FILT+ has a typical source impedance of
250 k and any current drawn from this pin will alter device performance.
Quiescent Voltage ( Output ) - Filter connection for internal quiescent reference voltage, typi-
cally 50% of VA. Capacitors must be connected from VQ to analog ground, as shown in
Figure 4. VQ is not intended to supply external current. VQ has a typical source impedence of
250 k and any current drawn from this pin will alter device performance.
Reference Ground ( Input ) - Ground reference for the internal sampling circuits. Must be con-
nected to analog ground.
teristics specifications table.
Ground ( Input ) - Ground Reference.
Analog Power ( Input ) - Analog power supply. Typically 3 to 5 VDC.
Mute Control ( Output ) - The Mute Control pin goes high during power-up initialization, reset,
muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is
intended to be used as a control for an external mute circuit to prevent the clicks and pops that
can occur in any single supply system. Use of Mute Control is not mandatory but recommended
for designs requiring the absolute minimum in extraneous clicks and pops.
DIF1
0
0
1
1
.
DIF0
0
1
0
1
Table 4. Digital Interface Format - DIF1 and DIF0
I
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
2
S, up to 24-bit data
DESCRIPTION
FORMAT
1
0
2
3
FIGURE
16
17
18
19
CS4340
15