CS4340-KS Cirrus Logic Inc, CS4340-KS Datasheet

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CS4340-KS

Manufacturer Part Number
CS4340-KS
Description
D/A Converter (D-A) IC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CS4340-KS

Resolution (bits)
24bit
Data Interface
Serial
No. Of Pins
16
Update Rate
96kSPS
Mounting Type
Surface Mount
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5V
No. Of Bits
24 Bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
101 dB Dynamic Range
91 dB THD+N
Low Clock Jitter Sensitivity
+3 V to +5 V Power Supply
Filtered Line Level Outputs
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
30 mW with 3 V supply
Popguard
and Pops
I
SDATA
LRCK
RST
®
Technology for Control of Clicks
24-Bit, 96 kHz Stereo DAC for Audio
SCLK/DEM1
DIF0 DIF1
Interface
Serial
Input
Interpolation
Interpolation
Filter
Filter
De-emphasis
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
DEM0
MCLK
Copyright
Description
The CS4340 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4340 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power, and oper-
ates over a wide power supply range. The features of the
CS4340 are ideal for DVD players, CD players, set-top
box and automotive systems.
ORDERING INFORMATION
(All Rights Reserved)
CS4340-KS
CS4340-BS
CDB4340
DAC
DAC
Mute Control
Cirrus Logic, Inc. 2000
External
MUTEC
Analog Filter
Analog Filter
16-pin SOIC, -10 to 70 °C
16-pin SOIC, -40 to 85 °C
Evaluation Board
CS4340
AOUTL
AOUTR
DS297PP3
NOV ‘00
1

Related parts for CS4340-KS

CS4340-KS Summary of contents

Page 1

... The CS4340 accepts data at audio sample rates from 2 kHz to 100 kHz, consumes very little power, and oper- ates over a wide power supply range. The features of the CS4340 are ideal for DVD players, CD players, set-top box and automotive systems. ORDERING INFORMATION CS4340-KS CS4340-BS CDB4340 DEM0 MUTEC External ...

Page 2

... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 ® Transient Control ............................................................ 16 ............................................. 19 CS4340 .............................. 17 DS297PP3 ...

Page 3

... Figure 14. Maximum Loading .................................................................................... 18 Figure 15. Power vs. Sample Rate (VA = 5V) ........................................................... 18 Figure 16. CS4340 Format 0 (I Figure 17. CS4340 Format 1 ..................................................................................... 19 Figure 18. CS4340 Format 2 ..................................................................................... 20 Figure 19. CS4340 Format 3 ..................................................................................... 20 Figure 20. De-Emphasis Curve ................................................................................. 21 Figure 21. FFT 0 dB input, BRM ................................................................ 22 Figure 22. FFT -60 dB input, BRM ............................................................. 22 Figure 23. FFT Idle Noise, BRM 3V................................................................. 22 Figure 24 ...

Page 4

... LIST OF TABLES Table 1. Internal Serial Clock Mode .......................................................................... 14 Table 2. External Serial Clock Mode ......................................................................... 14 Table 3. Common Master Clock Frequencies ........................................................... 14 Table 4. Digital Interface Format - DIF1 and DIF0 ................................................... 15 4 CS4340 DS297PP3 ...

Page 5

... Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Interchannel Isolation Notes: 1. CS4340-KS parts are tested at 25 °C and Min/Max performance numbers are guaranteed across the specified temperature range One-half LSB of triangular PDF dither is added to data. DS297PP3 (Test conditions (unless otherwise specified): T ...

Page 6

... Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Interchannel Isolation Notes: 3. CS4340-BS parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, T taken at 25 °C. 6 (Continued) Base-rate Mode ...

Page 7

... kHz - Min Typ Max 0.63•VA 0.7•VA 0.77•VA - 0.5• 0 100 - 100 L High-Rate Mode Typ Max Min Typ - .4535 - - - - .4998 +.08 -0. .577 - - - ±1.39/ ±0.23/Fs - +.2/-.1 - +.05/-.14 (Note 8) - +0/-.22 CS4340 Units Vpp VDC dB ppm/° Max Unit - Fs .4621 Fs .4982 Fs 0 ...

Page 8

... Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 4. Increasing the capacitance will also increase the PSRR. DIGITAL CHARACTERISTICS 5.5 V) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current 8 CS4340-KS Symbol Min normal operation power-down state (Note 9) ...

Page 9

... Parameters DC Power Supply DS297PP3 (AGND = 0 V; all voltages with respect to ground.) Symbol Min VA -0 -0.3 IND T - -65 stg (AGND = 0V; all voltages with respect to Symbol Min VA 2.7 CS4340 Max Units 6.0 V ±10 mA VA+0.4 V 125 °C 150 °C Typ Max Units 5.0 5 ...

Page 10

... V - 5.5 V; Inputs: Logic Logic -40 to 85°C) A Symbol Base-Rate Mode Fs High-Rate Mode MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh t sclkw t sclkw t slrd t slrs t sdlrs t sdh (Note 11) (Note 12) t sclkw t sclkr t sdlrs t sdh t sdh CS4340 Min Typ Max 100 10 - 1000 10 - 1000 21 - 1000 21 - 1000 31 - 1000 31 - 1000 ...

Page 11

... LRCK SCLK SDATA *INTERNAL SCLK *The SCLK pulses shown are internal to the CS4340. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4340. DS297PP3 t slrs t slrd t sdlrs Figure 1. External Serial Mode Input Timing LRCK t sclkr SDATA t t sdlrs sdh Figure 2 ...

Page 12

... AGND 0.1 µF 1 µ 3.3 µF 560 15 AOUTL + 10 k CS4340 MUTEC 16 9 FILT 0.1 µF .1 µF 1 µ REF_GND 3.3 µF 560 12 AOUTR + Figure 4. Typical Connection Diagram Left Audio Output OPTIONAL MUTE CIRCUIT + 1 µF Right Audio Output 560 560 S L CS4340 DS297PP3 ...

Page 13

... DIF1-0 pins as shown in Figures 16-19. Opera- tion in this mode is identical to operation with an external serial clock synchronized with LRCK. External Serial Clock Mode - The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. ...

Page 14

... Table 3. Common Master Clock Frequencies DESCRIPTION Disabled 44.1kHz 48kHz 32kHz DESCRIPTION MCLK (MHz) BRM 256x 384x 8.1920 12.2880 16.3840 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 - - - - - - CS4340 512x - - - DS297PP3 ...

Page 15

... DS297PP3 . DIF1 DIF0 DESCRIPTION 24-bit data 0 1 Left Justified 24-bit data 1 0 Right Justified, 24-bit Data 1 1 Right Justified, 16-bit Data Table 4. Digital Interface Format - DIF1 and DIF0 CS4340 FORMAT FIGURE ...

Page 16

... APPLICATIONS 4.1 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power arrange- ment with VA connected to a clean supply. Decou- pling capacitors should be located as close to the device package as possible ...

Page 17

... INTERPOLATION FILTER RESPONSE PLOTS Figure 5. Base-Rate Stopband Rejection Figure 7. Base-Rate Transition Band (Detail) Figure 9. High-Rate Stopband Rejection DS297PP3 Figure 6. Base-Rate Transition Band Figure 8. Base-Rate Passband Ripple Figure 10. High-Rate Transition Band CS4340 17 ...

Page 18

... Figure 11. High-Rate Transition Band (Detail) AGND 125 100 75 Safe Operating 50 Region 25 2 Resistive Load -- R Figure 14. Maximum Loading 18 Figure 12. High-Rate Passband Ripple 3.3 µF + AOUTx R L Figure 13. Output Test Load Figure 15. Power vs. Sample Rate (VA = 5V) CS4340 V out Sample Rate (kHz) DS297PP3 100 ...

Page 19

... INT SCLK = MCLK/LRCK = 512, 256 or 128 INT SCLK = MCLK/LRCK = 384 or 192 DS297PP3 + LSB MSB - 24-Bit Data Data Valid on Rising Edge of SCLK Figure 16. CS4340 Format LSB MSB - Left Justified 24-Bit Data Data Valid on Rising Edge of SCLK Figure 17. CS4340 Format 1 CS4340 Right Channel +5 +4 ...

Page 20

... INT SCLK = MCLK/LRCK = 384 or 192 Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period Figure 18. CS4340 Format Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period Figure 19. CS4340 Format 3 ...

Page 21

... Gain dB 0dB -10dB 7. ANALOG PERFORMANCE PLOTS The following CS4340 Analog Performance Plots were taken from the CDB4340 evaluation board using the Audio Precision Dual Domain System Two Cascade. All Base Rate Mode (BRM) plots were taken kHz sample rate with kHz bandwidth using a 20 kHz low-pass brick- DS297PP3 T1=50 µ ...

Page 22

... Figure 24. Fade-to-Noise Linearity, BRM -85 -86 -87 -88 -89 -90 -91 -92 -93 d -94 B -95 r -96 A -97 -98 -99 -100 -101 -102 -103 -104 -105 -25 -20 -15 - Figure 26. THDN vs Freq, BRM 10k 12k 14k Hz -80 -70 -60 -50 -40 -30 dBFS 50 100 200 500 CS4340 16k 18k 20k -20 - 10k 20k DS297PP3 ...

Page 23

... Figure 30. Fade-to-Noise Linearity, BRM -85 -86 -87 -88 -89 -90 -91 -92 -93 d -94 B -95 r -96 A -97 -98 -99 -100 -101 -102 -103 -104 -105 20 -25 -20 -15 - Figure 32. THDN vs Freq, BRM 10k 12k 14k Hz -90 -80 -70 -60 -50 -40 -30 dBFS 50 100 200 500 CS4340 16k 18k 20k -20 - 10k 20k 23 ...

Page 24

... Figure 36. Fade-to-Noise Linearity, HRM -85 -86 -87 -88 -89 -90 -91 -92 - -95 -96 A -97 -98 -99 -100 -101 -102 -103 -104 -105 -25 -20 -15 - Figure 38. THDN vs Freq, HRM 10k 15k 20k 25k 30k Hz -80 -70 -60 -50 -40 -30 dBFS 50 100 200 500 CS4340 35k 40k -20 -10 +0 10k 20k 40k DS297PP3 ...

Page 25

... Figure 42. Fade-to-Noise Linearity, HRM -85 -86 -87 -88 -89 -90 -91 -92 - -95 -96 A -97 -98 -99 -100 -101 -102 -103 -104 -105 -25 -20 -15 - Figure 44. THDN vs Freq, HRM 10k 15k 20k 25k 30k Hz -80 -70 -60 -50 -40 -30 dBFS 50 100 200 500 CS4340 35k 40k -20 -10 +0 10k 20k 40k 25 ...

Page 26

... Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4340 Evaluation Board Datasheet 26 CS4340 DS297PP3 ...

Page 27

... JEDEC #: MS-012 Controling Dimension is Millimeters CS4340 c L MILLIMETERS MIN NOM MAX 1.35 1.63 1.75 0.10 0.15 0.25 0.33 0.41 0.51 0.19 0.20 0.25 9.80 9 ...

Page 28

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