CS4340-KS Cirrus Logic Inc, CS4340-KS Datasheet - Page 14

• Manufacturer Part Number: CS4340-KS
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4340-KS

• Resolution (bits): 24bit
• Data Interface: Serial
• No. Of Pins: 16
• Update Rate: 96kSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• No. Of Bits: 24 Bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14
DEM1 and DEM0
LRCK
MCLK
3 & 8 De-emphasis Control ( Input ) - Implementation of the standard 15 s/50 s digital de-emphasis
4
5
filter response, Figure 20, requires reconfiguration of the digital filter to maintain the proper filter
response for 32, 44.1 or 48 kHz sample rates. When using Internal Serial Clock Mode, as
described above, Pin 3 is available for de-emphasis control, DEM1, and all de-emphasis filters
are available, Table 3. When using External Serial Clock Mode, as described above, Pin 3 is
not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is available,
Table 4. NOTE: De-emphasis is not available in High-Rate Mode.
Left/Right Clock ( Input ) - The Left/Right clock determines which channel is currently being
input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at
the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output
from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period
difference. The required relationship between the Left/Right clock, serial clock and serial data is
defined by the DIF1-0 pins. The options are detailed in Figures 16-19.
Master Clock ( Input ) - The master clock frequency must be either 256x, 384x or 512x the input
sample rate in Base Rate Mode (BRM) and either 128x or 192x the input sample rate in High
Rate Mode (HRM). Table 3 illustrates several standard audio sample rates and the required
master clock frequencies.
Sample
(kHz)
Rate
44.1
88.2
32
48
64
96
12.2880
11.2896
4.0960
5.6448
6.1440
8.1920
128x
Table 3. Common Master Clock Frequencies
DEM1
0
0
1
1
Table 2. External Serial Clock Mode
Table 1. Internal Serial Clock Mode
DEMO
HRM
0
1
12.2880
16.9344
18.4320
6.1440
8.4672
9.2160
DEMO
192x
0
1
0
1
Disabled
44.1kHz
DESCRIPTION
Disabled
44.1kHz
48kHz
32kHz
MCLK (MHz)
12.2880
11.2896
DESCRIPTION
8.1920
256x
-
-
-
12.2880
16.9344
18.4320
BRM
384x
-
-
-
16.3840
22.5792
24.5760
512x
CS4340
-
-
-
DS297PP3