P89V51RC2FN NXP Semiconductors, P89V51RC2FN Datasheet - Page 20

• Manufacturer Part Number: P89V51RC2FN
• Description: IC, MCU 8BIT 80C51 32K FLASH, DIP40
• Manufacturer: NXP Semiconductors

Specifications of P89V51RC2FN

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 32
• Program Memory Size: 32KB
• Ram Memory Size: 1KB
• Cpu Speed: 33MHz
• Oscillator Type: External Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Package: 40PDIP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.3.1 Flash organization
6.3.2 Boot block (block 1)
6.3 Flash memory IAP
Table 10.
Not bit addressable; Reset value 00H
Table 11.
The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP
capability, in a second 8 kB block, is provided to allow the user code to be programmed
in-circuit through the serial port. There are three methods of erasing or programming of
the flash memory that may be used. First, the flash may be programmed or erased in the
end-user application by calling low-level routines through a common entry point (IAP).
Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call
low-level routines through the same common entry point that can be used by the end-user
application. Third, the flash may be programmed or erased using the parallel method by
using a commercially available EPROM programmer which supports this device.
When the microcontroller programs its own flash memory, all of the low level details are
handled by code that is contained in block 1. A user program calls the common entry point
in the block 1 with appropriate parameters to accomplish the desired operation. Boot block
operations include erase user code, program user code, program security bits, etc.
Bit
7 to 4
3
2
1
0
Bit
Symbol
Fig 7. Dual data pointer organization
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
-
AUXR1 - Auxiliary register 1 (address A2H) bit description
Symbol
-
GF2
0
-
DPS
7
DPS = 0
DPS = 1
AUXR1 / bit0
-
Rev. 05 — 12 November 2009
DPS
6
DPTR0
DPTR1
Description
Reserved for future use. Should be set to ‘0’ by user programs.
General purpose user-defined flag.
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
Reserved for future use. Should be set to ‘0’ by user programs.
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
-
5
DPH
83H
-
P89V51RB2/RC2/RD2
4
DPL
82H
8-bit microcontrollers with 80C51 core
DPTR1
DPTR0
GF2
3
external data memory
0
2
002aaa518
-
© NXP B.V. 2009. All rights reserved.
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DPS
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0