P87LPC761BN NXP Semiconductors, P87LPC761BN Datasheet - Page 20

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P87LPC761BN

Manufacturer Part Number
P87LPC761BN
Description
IC, MCU 8BIT 80C51 2K OTP, DIP16
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P87LPC761BN

Controller Family/series
(8051) 8052
Core Size
8bit
No. Of I/o's
14
Program Memory Size
2KB
Ram Memory Size
128Byte
Cpu Speed
20MHz
Oscillator Type
External, Internal
No. Of Timers
2
Digital
RoHS Compliant
Package
16PDIP
Device Core
80C51
Family Name
87LP
Maximum Speed
20 MHz
Ram Size
128 Byte
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
14
Interface Type
I2C/UART
Operating Temperature
0 to 70 °C
Number Of Timers
2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P87LPC761BN
Manufacturer:
TI
Quantity:
6
Philips Semiconductors
External Interrupt Inputs
The P87LPC761 has one individual interrupt input as well as the
Keyboard Interrupt function. The latter is described separately in this
section. The interrupt input is identical to those present on the
standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT0 in Register TCON. If
IT0 = 0, external interrupt 0 is triggered by a detected low at the
INT0 pin. If IT0 = 1, external interrupt 0 is edge-triggered. In this
mode if successive samples of the INT0 pin show a high in one
cycle and a low in the next cycle, interrupt request flag IE0 in TCON
is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 6 CPU Clocks to
ensure proper sampling. If the external interrupt is
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EX0
KBF
EC2
EC1
IE0
Figure 9. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources
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ATN
TF0
ET0
TF1
ET1
EI2
ES
17
transition-activated, the external source has to hold the request pin
high for at least one machine cycle, and then hold it low for at least
one machine cycle. This is to ensure that the transition is seen and
that interrupt request flag IE0 is set. IE0 is automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must
hold the request active until the requested interrupt is actually
generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is
not necessary to clear the interrupt flag IE0 when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the P87LPC761 is put into
Power Down or Idle mode, the interrupt will cause the processor to
wake up and resume operation. Refer to the section on Power
Reduction Modes for details.
(FROM IEN0
REGISTER)
EA
P87LPC761
INTERRUPT
(IF IN POWER
TO CPU
WAKEUP
SU01570
DOWN)
Preliminary data

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