FM31L278-G Ramtron, FM31L278-G Datasheet - Page 13

• Manufacturer Part Number: FM31L278-G
• Description: FRAM, MPU SUPPORT, 256K, RTC, SOIC14
• Manufacturer: Ramtron

Specifications of FM31L278-G

• Memory Size: 256Kbit
• Nvram Features: RTC
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 14
• Operating Temperature Range: -40°C To +85°C
• Package / Case: SOIC
• Mounting Style: SMD/SMT
• Memory Configuration: 32768 X 8
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.6 V or 2.9 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Yes
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1500 uA
• Power Fail Detection: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 2.0
Jan. 2011
0Ch
RC
CC
C2P
C1P
0Bh
SNL
FC
WP1-0
VBC
VTP
0Ah
WDE
WDT4-0
Event Counter Control
Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by
C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of
Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is
“don’t care” when CC=1. Battery-backed, read/write.
CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don’t care” when CC=1. The value
of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write.
CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may
inadvertently increment if C1P is changed. Battery-backed, read/write.
Companion Control
Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be
cleared once set to 1. Nonvolatile, read/write.
Fast Charge: Setting FC to ‘1’ (and VBC=1) causes a ~1 mA trickle charge current to be supplied on V
Clearing VBC to ‘0’ disables the charge current. Nonvolatile, read/write.
Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.
VBAK Charger Control. Setting VBC to ‘1’ (and FC=0) causes a ~80 µA (1 mA if FC=1) trickle charge current to
be supplied on V
VTP select. This bit controls the reset trip point for the low VDD reset function. Nonvolatile, read/write.
Watchdog Control
Watchdog Enable. When WDE=1, a watchdog timer fault will cause the /RST signal to go active. When WDE = 0
the timer runs but has no effect on /RST, however the WTR flag will be set when a fault occurs. Note as the timer
is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog
timeout interval occurs. Nonvolatile, read/write.
Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.
WDE
SNL
D7
D7
D7
-
Write protect addresses
None
Bottom 1/4
Bottom 1/2
Full array
Trip Voltage
Watchdog timeout
Invalid – default 100 ms
100 ms
200 ms
300 ms
2000 ms
2100 ms
2200 ms
2900 ms
3000 ms
Disable counter
2.6V
2.9V
.
.
.
.
.
.
D6
D6
D6
BAK
-
-
-
. Clearing VBC to ‘0’ disables the charge current. Nonvolatile, read/write.
VTP
0
1
D5
D5
D5
FC
-
-
WP1
0
0
1
1
WDT4 WDT3 WDT2 WDT1 WDT0
WDT4
WP1
D4
D4
D4
0
0
0
0
1
1
1
1
1
1
-
WP0
0
1
0
1
FM31L278/L276/L274/L272 - 3V I2C Companion
0
0
0
0
0
0
0
1
1
1
WDT3
WP0
D3
D3
D3
RC
0
0
0
0
1
1
1
1
1
1
WDT2
0
0
1
1
0
0
1
0
1
1
VBC
D2
CC
D2
D2
0
1
0
1
0
1
0
1
0
1
WDT1
C2P
D1
D1
D1
-
Page 13 of 26
BAK
WDT0
VTP
C1P
D0
D0
.
D0