LM5642MTC National Semiconductor, LM5642MTC Datasheet - Page 18

• Manufacturer Part Number: LM5642MTC
• Description: IC, DUAL SYNC BUCK CONVERTER, 28-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM5642MTC

• Primary Input Voltage: 36V
• No. Of Outputs: 2
• Output Voltage: 32.4V
• Output Current: 20A
• No. Of Pins: 28
• Operating Temperature Range: -40°C To +125°C
• Power Dissipation Pd: 1.1W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Where Vfb = 1.238V. Although increasing the value of R1 and
R2 will increase efficiency, this will also decrease accuracy.
Therefore, a maximum value is recommended for R2 in order
to keep the output within .3% of Vnom. This maximum R2
value should be calculated first with the following equation:
Where 200nA is the maximum current drawn by FBx pin.
Example: Vnom = 5V, Vfb = 1.2364V, Ifbmax = 200nA.
Choose 60K
The Cycle Skip and Dropout modes of the LM5642 series
regulate the minimum and maximum output voltage/duty cy-
cle that the converter can deliver. Both modes check the
voltage at the COMP pin. Minimum output voltage is deter-
mined by the Cycle Skip Comparator. This circuitry skips the
high side FET ON pulse when the COMP pin voltage is below
0.5V at the beginning of a cycle. The converter will continue
to skip every other pulse until the duty cycle (and COMP pin
voltage) rise above 0.5V, effectively halving the switching fre-
quency.
Maximum output voltage is determined by the Dropout cir-
cuitry, which skips the low side FET ON pulse whenever the
COMP pin voltage exceeds the ramp voltage derived from the
current sense. Up to three low side pulses may be skipped in
a row before a minimum on-time pulse must be applied to the
low side FET.
Figure 10
respect to input voltage that will keep the converter from en-
tering either Skip Cycle or Dropout mode.
For input voltages below 5.5V, VLIN5 must be connected to
Vin through a small resistor (approximately 4.7 ohm). This will
ensure that VLIN5 does not fall below the UVLO threshold.
shows the range of ouput voltage (for Io = 3A) with
FIGURE 9. Output Voltage Setting
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Output Capacitor Selection
In applications that exhibit large, fast load current swings, the
slew rate of such a load current transient will likely be beyond
the response speed of the regulator. Therefore, to meet volt-
age transient requirements during worst-case load transients,
special consideration should be given to output capacitor se-
lection. The total combined ESR of the output capacitors must
be lower than a certain value, while the total capacitance must
be greater than a certain value. Also, in applications where
the specification of output voltage regulation is tight and ripple
voltage must be low, starting from the required output voltage
ripple will often result in fewer design iterations.
ALLOWED TRANSIENT VOLTAGE EXCURSION
The allowed output voltage excursion during a load transient
(ΔVc_s) is:
Where ±δ% is the output voltage regulation window and ±ε%
is the output voltage initial accuracy.
Example: Vnom = 5V, δ% = 7%, ε% = 3.4%, Vrip = 40mV peak
to peak.
MAXIMUM ESR CALCULATION
Unless the rise and fall times of a load transient are slower
than the response speed of the control loop, if the total com-
bined ESR (Re) is too high, the load transient requirement will
not be met, no matter how large the capacitance.
The maximum allowed total combined ESR is:
Since the ripple voltage is included in the calculation of
ΔVc_s, the inductor ripple current should not be included in
the worst-case load current excursion. Simply use the worst-
case load current excursion for ΔIc_s.
Example: ΔVc_s = 160 mV, ΔIc_s = 3A. Then Re_max = 53.3
mΩ.
FIGURE 10. Output Voltage Range
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