ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 59

• Manufacturer Part Number: ST7FLITE05Y0B6
• Description: IC, 8BIT MCU, ST7, 16MHZ, DIP-16
• Manufacturer: FARNELL

Specifications of ST7FLITE05Y0B6

• Controller Family/series: ST7
• No. Of I/o's: 13
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Interface: SPI
• Core Size: 8 Bit
• Program Memory Size: 1.5 Kb
• Peripherals: ADC, PWM, Timer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
11.3.2 Main Features
■
■
■
■
■
■
■
■
■
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
Figure 37. Serial Peripheral Interface Block Diagram
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
SS
/2 max. slave mode frequency (see note)
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
/4 max.)
Data/Address Bus
Read
Write
software overhead for clearing status flags and to
initiate the next transmission sequence.
11.3.3 General Description
Figure 37
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
3 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
CONTROL
SPR2
ST7LITE0xY0, ST7LITESxY0
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
SSI
0
59/124
0
1