ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 34

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ST7FLITE05Y0B6

Manufacturer Part Number
ST7FLITE05Y0B6
Description
IC, 8BIT MCU, ST7, 16MHZ, DIP-16
Manufacturer
FARNELL
Datasheet

Specifications of ST7FLITE05Y0B6

Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
2
Interface
SPI
Core Size
8 Bit
Program Memory Size
1.5 Kb
Peripherals
ADC, PWM, Timer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE05Y0B6
Manufacturer:
ST
Quantity:
20 000
ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
8.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
V
ply voltage (V
for falling voltage is lower than the V
ence value for rising voltage in order to avoid par-
asitic detection (hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
Figure 21. Using the AVD to Monitor V
34/124
1
IT+(AVD)
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
reference value and the V
V
AVD
DD
). The V
0
IT-(AVD)
1
reference value
IT+(AVD)
DD
INTERRUPT Cleared by
IT-(AVD)
main sup-
V
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
DD
hyst
refer-
reset
and
RESET
8.4.2.1 Monitoring the V
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
V
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See
The interrupt on the rising edge is used to inform
the application that the V
IT-(AVD)
section 15.1 on page
threshold (AVDF bit is set).
Figure
21.
1
DD
INTERRUPT Cleared by
DD
112).
warning state is over
Main Supply
hardware
0
IT+(LVD)
or

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