ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 51

• Manufacturer Part Number: ST7FLITE05Y0B6
• Description: IC, 8BIT MCU, ST7, 16MHZ, DIP-16
• Manufacturer: FARNELL

Specifications of ST7FLITE05Y0B6

• Controller Family/series: ST7
• No. Of I/o's: 13
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Interface: SPI
• Core Size: 8 Bit
• Program Memory Size: 1.5 Kb
• Peripherals: ADC, PWM, Timer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LITE TIMER (Cont’d)
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the value of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
Figure 33. Input Capture Timing Diagram
Mode
SLOW
WAIT
ACTIVE HALT
HALT
LTICR REGISTER
8-bit COUNTER
ICF FLAG
LTIC PIN
f
OSC
Description
f
No effect on Lite timer
(this peripheral is driven directly by
f
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
CPU
/32
OSC
/32)
01h
(@ 8 MHz f
4µs
02h
xxh
OSC
)
03h
04h
11.1.5 Interrupts
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
Timebase and IC events generate an interrupt if
the enable bit is set in the LTCSR register and the
interrupt mask in the CC register is reset (RIM in-
struction).
Timebase
Event
IC Event
05h
Interrupt
Event
04h
06h
Event
Flag
TBF
ICF
ST7LITE0xY0, ST7LITESxY0
07h
Control
Enable
TBIE
ICIE
Bit
LTIC REGISTER
07h
from
Wait
CLEARED
Exit
READING
Yes
BY S/W
from
Exit
Halt
No
t
Active-
from
Exit
Halt
Yes
51/124
No
1