SAK-C164CI-8EM Infineon Technologies, SAK-C164CI-8EM Datasheet - Page 19

16BIT MCU, 64K OTP, 4K RAM, CAN, 20MHZ

SAK-C164CI-8EM

Manufacturer Part Number
SAK-C164CI-8EM
Description
16BIT MCU, 64K OTP, 4K RAM, CAN, 20MHZ
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAK-C164CI-8EM

No. Of I/o's
59
Ram Memory Size
2KB
Cpu Speed
20MHz
No. Of Timers
5
Digital Ic Case Style
MQFP
Supply Voltage
RoHS Compliant
Core Size
16bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Controller Family/series
C164CI
Rohs Compliant
Yes

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C164CI/SI
C164CL/SL
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C164CI instruction set which includes
the following instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
15
V2.0, 2001-05

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