LPC2119FBD64 NXP Semiconductors, LPC2119FBD64 Datasheet - Page 13

• Manufacturer Part Number: LPC2119FBD64
• Description: 16/32BIT MCU ARM7, 128K FLASH, 64LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC2119FBD64

• No. Of I/o's: 46
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case: RoHS Compliant
• Core Size: 32bit
• Program Memory Size: 128KB
• Oscillator Type: External Only
• Controller Family/series: LPC21xx
• Rohs Compliant: Yes
• Data Bus Width: 16 bit, 32 bit
• Program Memory Type: Flash
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, JTAG, SPI, SSP, UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / Rohs Status: Details

NXP Semiconductors
Product data sheet
LPC2109_2119_2129_6
6.5.1 Interrupt sources
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
Table 4
one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Table 4.
Block
WDT
-
ARM Core
ARM Core
Timer 0
Timer 1
UART0
UART1
PWM0
I
SPI0
SPI1 and SSP
PLL
RTC
2
C-bus
lists the interrupt sources for each peripheral function. Each peripheral device has
Interrupt sources
[1]
Flag(s)
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
EmbeddedICE, DbgCommRx
EmbeddedICE, DbgCommTx
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
SPIF, MODF
SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
PLL Lock (PLOCK)
RTCCIF (Counter Increment), RTCALF (Alarm)
Rev. 06 — 10 December 2007
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
VIC channel #
0
1
2
3
4
5
6
7
8
9
10
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