LPC1226FBD48/301 NXP Semiconductors, LPC1226FBD48/301 Datasheet - Page 25
![MCU, 96K FLASH, CORTEX-M0, 48LQFP](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
LPC1226FBD48/301
Manufacturer Part Number
LPC1226FBD48/301
Description
MCU, 96K FLASH, CORTEX-M0, 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1224FBD48201.pdf
(60 pages)
Specifications of LPC1226FBD48/301
Rohs Compliant
YES
Featured Product
LPC122x Cortex-M0 Microcontrollers
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
45MHz
Connectivity
I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
LPC1200
No. Of I/o's
39
Ram Memory Size
8KB
Cpu Speed
30MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5161
LPC1226FBD48/301
LPC1226FBD48/301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1226FBD48/301
Manufacturer:
ROHM
Quantity:
12 000
Company:
Part Number:
LPC1226FBD48/301,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC122X
Objective data sheet
7.18.1.3 Watchdog oscillator
7.18.5.1 Sleep mode
7.18.2 System PLL
7.18.3 Clock output
7.18.4 Wake-up process
7.18.5 Power control
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this
document.
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is 40 %.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
The LPC122x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
The LPC122x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
The LPC122x support a variety of power control features. There are three special modes
of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down
mode. The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
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