PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 46
![IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC24FJ256GA106-I/MR
Manufacturer Part Number
PIC24FJ256GA106-I/MR
Description
IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ256GA106-IPT.pdf
(59 pages)
6.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ256GA106-I/MR
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Core Size
16 Bit
Program Memory Size
256KB
Peripherals
ADC, Comparator, PWM, RTC, Timer
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC24FJXXXDA1/DA2/GB2/GA3
5.2.7
The READP command instructs the programming
executive to read N 24-bit words of code memory,
including Configuration Words, starting from the 24-bit
address specified by Addr_MSB and Addr_LS. This
command can only be used to read 24-bit data. All data
returned in response to this command uses the packed
data format described in
Format”.
Expected Response (2 + 3 * N/2 Words for N Even):
Expected Response (4 + 3 * (N – 1)/2 Words for N Odd):
DS39970B-page 46
15
Opcode
Length
N
Reserved
Addr_MSB
Addr_LS
Note:
Opcode
1200h
2 + 3 * N/2
Least Significant Program Memory Word 1
...
Least Significant Data Word N
1200h
4 + 3 * (N – 1)/2
Least Significant Program Memory Word 1
...
MSB of Program Memory Word N (zero-padded)
Field
Reserved
12 11
READP COMMAND
Reading unimplemented memory will
cause the programming executive to
reset. Ensure that only memory locations
present on a particular device are
accessed.
2h
4h
Number of 24-bit instructions to read
(max. of 32768)
0h
MSB of 24-bit source address
Least Significant 16 bits of 24-bit
source address
Addr_LS
Section 5.2.2 “Packed Data
8 7
N
Description
Length
Addr_MSB
0
5.2.8
The PROGC command instructs the programming
executive to program a single Device ID register
located at the specified memory address.
After the specified data word has been programmed to
code memory, the programming executive verifies the
programmed data against the data in the command.
Expected Response (2 Words):
15
Opcode
Length
Reserved
Addr_MSB
Addr_LS
Data
Opcode
Field
1400h
0002h
Reserved
12 11
PROGC COMMAND
4h
4h
0h
MSB of the 24-bit destination address
Least Significant 16 bits of the 24-bit
destination address
8-bit data word
Addr_LS
2010 Microchip Technology Inc.
Data
8 7
Description
Length
Addr_MSB
0