PIC16LF1827-I/P Microchip Technology, PIC16LF1827-I/P Datasheet - Page 99

• Manufacturer Part Number: PIC16LF1827-I/P
• Description: IC, 8BIT MCU, PIC16LF, 32MHZ, DIP-18
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-I/P

• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4kWords
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.5.9
The PIR4 register contains the interrupt flag bits, as
shown in Register 8-9.
REGISTER 8-9:
TABLE 8-1:
 2010 Microchip Technology Inc.
INTCON
OPTION_REG
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Note 1:
(1)
(1)
(1)
(1)
Name
U-0
—
— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
PIC16F/LF1827 only.
This register is only available on PIC16F/LF1827.
PIR4 REGISTER
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress
TMR1GIE
TMR1GIF
WPUEN
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
U-0
—
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
INTEDG
(1)
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
—
—
U-0
—
TMR0CS
TMR0IE
CCP4IE
CCP4IF
RCIE
C1IE
RCIF
Bit 5
C1IF
—
—
U-0
Preliminary
—
TMR0SE
CCP3IE
CCP3IF
INTE
TXIE
EEIE
Bit 4
TXIF
EEIF
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
TMR6IE
SSP1IE
TMR6IF
BCL1IE
SSP1IF
BCL1IF
IOCIE
U-0
Bit 3
PSA
—
—
—
Note 1: The PIR4 register is available only on the
PIC16F/LF1826/27
2: Interrupt flag bits are set when an inter-
TMR0IF
CCP1IE
CCP1IF
Bit 2
PS2
PIC16F/LF1827 device.
rupt condition occurs, regardless of the
state of its corresponding enable bit or the
Global Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
—
—
—
—
—
—
U-0
—
TMR2IE
TMR4IE
TMR2IF
TMR4IF
BCL2IE
BCL2IF
Bit 1
INTF
PS1
—
—
(1)
R/W/HS-0/0
BCL2IF
CCP2IE
CCP2IF
TMR1IE
TMR1IF
SSP2IE
SSP2IF
IOCIF
Bit 0
PS0
—
—
DS41391C-page 99
(1)
(1)
R/W/HS-0/0
SSP2IF
Register
on Page
177
91
92
93
94
95
96
97
98
99
bit 0