PIC16LF1827-I/P Microchip Technology, PIC16LF1827-I/P Datasheet - Page 25

• Manufacturer Part Number: PIC16LF1827-I/P
• Description: IC, 8BIT MCU, PIC16LF, 32MHZ, DIP-18
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-I/P

• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4kWords
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 3-3:
Legend:
00Ah
00Bh
00Ch
00Dh
00Eh
01Ah
01Bh
01Ch
01Dh
01Eh
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Fh
020h
06Fh
070h
07Fh
Note 1:
CPSCON0
CPSCON1
T1GCON
BANK0
STATUS
PCLATH
INTCON
96 Bytes
General
Purpose
Register
PORTA
PORTB
TMR1H
T1CON
T2CON
FSR0L
FSR0H
FSR1L
FSR1H
WREG
PIR3
PIR4
TMR1L
INDF0
INDF1
TMR0
TMR2
PIR1
PIR2
Available only on PIC16F/LF1827.
BSR
PCL
PR2
—
—
—
—
= Unimplemented data memory locations, read as ‘0’
(1)
(1)
PIC16F/LF1826/27 MEMORY MAP, BANKS 0-7
08Ah
08Bh
08Ch
08Dh
08Eh
09Ah
09Bh
09Ch
09Dh
09Eh
0A0h
0EFh
0FFh
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Fh
0F0h
OSCTUNE
OSCSTAT
WDTCON
70h – 7Fh
OSCCON
Accesses
ADRESL
ADRESH
ADCON0
ADCON1
BANK1
STATUS
PCLATH
INTCON
OPTION
80 Bytes
General
Purpose
Register
FSR0L
FSR0H
FSR1L
FSR1H
WREG
PIE3
PIE4
INDF0
INDF1
TRISA
TRISB
PCON
BSR
PIE1
PIE2
PCL
—
—
—
—
(1)
(1)
10Ah
10Bh
10Ch
10Dh
10Eh
11Ah
11Bh
11Ch
11Dh
11Eh
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Fh
120h
16Fh
170h
17Fh
CM1CON0
CM1CON1
CM2CON0
CM2CON1
DACCON0
DACCON1
APFCON0
APFCON1
BORCON
70h – 7Fh
FVRCON
Accesses
STATUS
PCLATH
SRCON0
SRCON1
BANK2
INTCON
80 Bytes
CMOUT
General
Purpose
Register
FSR0L
FSR0H
FSR1L
FSR1H
WREG
INDF0
INDF1
LATA
LATB
PCL
BSR
—
—
—
—
—
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1EFh
1F0h
1FFh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
BAUDCON
80 Bytes
70h – 7Fh
EEADRH
SPBRGH
Accesses
BANK3
STATUS
PCLATH
ANSELA
ANSELB
EEADRL
EEDATH
EECON1
EECON2
SPBRGL
INTCON
EEDATL
Purpose
Register
RCREG
General
FSR0H
FSR1H
TXREG
RCSTA
FSR0L
FSR1L
WREG
TXSTA
INDF0
INDF1
PCL
BSR
—
—
—
—
—
(1)
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
26Fh
27Fh
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
220h
270h
Unimplemented
SSP2MASK
SSP2CON2
SSP2CON3
SSP2STAT
SSP2CON
SSP2BUF
SSP2ADD
SSP1MASK
SSP1CON2
SSP1CON3
SSP1STAT
Read as ‘0’
48 Bytes
SSP1ADD
SSP1CON
SSP1BUF
70h – 7Fh
Accesses
BANK4
STATUS
PCLATH
INTCON
Purpose
Register
General
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
WPUA
WPUB
PCL
BSR
—
—
—
—
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
282h
285h
287h
288h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
292h
293h
294h
295h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
280h
281h
283h
284h
286h
289h
290h
291h
296h
297h
298h
299h
Unimplemented
PSTR2CON
PWM2CON
CCPTMRS
CCP2CON
PWM1CON
PSTR1CON
CCPR2H
Read as ‘0’
CCP1CON
CCPR2L
CCP2AS
70h – 7Fh
CCPR1H
Accesses
BANK5
STATUS
PCLATH
CCPR1L
CCP1AS
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
(1)
(1)
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
Unimplemented
CCP3CON
CCP4CON
CCPR3H
CCPR4H
Read as ‘0’
CCPR3L
CCPR4L
70h – 7Fh
Accesses
BANK6
STATUS
PCLATH
INTCON
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
PCL
BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
(1)
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
Unimplemented
Read as ‘0’
CLKRCON
MDCARH
70h – 7Fh
MDCARL
Accesses
BANK7
STATUS
PCLATH
INTCON
MDCON
MDSRC
FSR0H
FSR1H
IOCBN
FSR0L
FSR1L
WREG
IOCBP
IOCBF
INDF0
INDF1
BSR
PCL
—
—
—
—
—
—
—
—
—
—
—
—