AS6C8016-55BIN ALLIANCE MEMORY, AS6C8016-55BIN Datasheet - Page 7
![SRAM, 8MB, 2.7-5.5V, 512KX16, TFBGA48](/photos/19/5/190585/ge48fbga07-40_sml.jpg)
AS6C8016-55BIN
Manufacturer Part Number
AS6C8016-55BIN
Description
SRAM, 8MB, 2.7-5.5V, 512KX16, TFBGA48
Manufacturer
ALLIANCE MEMORY
Datasheet
1.AS6C8016-55BIN.pdf
(12 pages)
Specifications of AS6C8016-55BIN
Memory Size
8Mbit
Access Time
55ns
Supply Voltage Range
2.7V To 5.5V
Memory Case Style
TFBGA
No. Of Pins
48
Operating Temperature Range
-40°C To +85°C
Operating Temperature Max
85°C
Memory Configuration
512K X 16
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WRITE CYCLE 3
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
6.t
LB#,UB#
Address
placed on the bus.
state.
OW
WE#
Dout
CE#
Din
NOVEMBER/2007, V 1.0
January 2007
NOVEMBER 2007
and t
WHZ
are specified with C
(LB#
,UB#
t
AS
Controlled)
L
512K X 16 BIT SUPER LOW POWER CMOS SRAM
= 5pF. Transition is measured ±500mV from steady state.
(4)
t
WHZ
(1,2,5,6)
Alliance Memory Inc.
WP
t
AW
must be greater than t
t
t
CW
WP
t
WC
t
BW
512K X 8 BIT LOW POWER CMOS SRAM
t
DW
High-Z
WHZ
Data Valid
+ t
DW
to allow the drivers to turn off and data to be
t
WR
t
DH
Page 7 of 12
AS6C8016