AM29F016D-90SF Spansion Inc., AM29F016D-90SF Datasheet - Page 24

IC, FLASH, 16MBIT, 90NS, SOIC-44

AM29F016D-90SF

Manufacturer Part Number
AM29F016D-90SF
Description
IC, FLASH, 16MBIT, 90NS, SOIC-44
Manufacturer
Spansion Inc.
Datasheet

Specifications of AM29F016D-90SF

Memory Type
Flash
Memory Size
16Mbit
Memory Configuration
2M X 8
Ic Interface Type
Parallel
Access Time
90ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
44
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the
quence”
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
22
section.
“Sector Erase Command Se-
D A T A
Am29F016D
S H E E T
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table
Notes:
1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5
toggling. See text.
changes to “1”. See text.
No
Figure 5. Toggle Bit Algorithm
Complete, Write
Reset Command
Read DQ7–DQ0
Read DQ7–DQ0
Read DQ7–DQ0
Program/Erase
Operation Not
10
Toggle Bit
Toggle Bit
= Toggle?
DQ5 = 1?
= Toggle?
START
Twice
shows the outputs for DQ3.
Yes
Yes
Yes
21444E9 November 16, 2009
(Notes
1, 2)
(Note
Operation Complete
No
No
Program/Erase

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