S29JL032H90TFI320 Spansion Inc., S29JL032H90TFI320 Datasheet - Page 14

• Manufacturer Part Number: S29JL032H90TFI320
• Description: IC, FLASH, 32MBIT, 90NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of S29JL032H90TFI320

• Memory Type: Flash
• Memory Size: 32Mbit
• Memory Configuration: 4M X 8 / 2M X 16
• Ic Interface Type: CFI, Parallel
• Access Time: 90ns
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: TSOP
• Data Bus Width: 8 bit, 16 bit
• Architecture: Boot Sector
• Interface Type: Conventional
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 2 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-48
• Rohs Compliant: YES
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.2
8.3
14
8.3.1
8.3.2
Requirements for Reading Array Data
Writing Commands/Command Sequences
Accelerated Program Operation
Autoselect Functions
To read array data from the outputs, the system must drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for
read access until the command register contents are altered.
Refer to the
timing diagram. I
array data.
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to V
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or
words. Refer to
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four.
Word Program Command Sequence on page 32
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 8.4 on page 19
the address bits required to uniquely select a sector.
a sector or the entire chip, or suspending/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the address bits required to uniquely
select a bank.
I
Characteristics on page 47
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at
the factory.
If the system asserts V
mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the
time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
operation. Note that V
programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result. See
information.
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on
DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to
Autoselect Command Sequence on page 32
CC2
in the DC Characteristics table represents the active current specification for the write mode.
IH
Read-Only Operations on page 47
. The BYTE# pin determines whether the device outputs array data in words or bytes.
Word/Byte Configuration on page 13
CC1
in
indicate the address space that each sector occupies. Similarly, a “sector address” is
HH
HH
DC Characteristics on page 44
must not be asserted on WP#/ACC for operations other than accelerated
on this pin, the device automatically enters the aforementioned Unlock Bypass
contains timing specification tables and timing diagrams for write operations.
S29JL032H
D a t a
for more information.
for timing specifications and to
has details on programming data to the device using both
HH
Command Definitions on page 31
for more information.
from the WP#/ACC pin returns the device to normal
represents the active current specification for reading
S h e e t
IL
, and OE# to V
Write Protect (WP#) on page 24
Autoselect Mode on page 21
S29JL032H_00_B8 August 31, 2009
Figure 17.1 on page 47
IH
Table 8.3 on page 17
.
has details on erasing
IL
. CE# is the power
AC
for related
and
Byte/
and
for the