LCMXO256C-5TN100C LATTICE SEMICONDUCTOR, LCMXO256C-5TN100C Datasheet - Page 176
![MACHXO PLD FLASH, SCRAM 1.8V, 256](/photos/19/0/190054/42334689_sml.jpg)
LCMXO256C-5TN100C
Manufacturer Part Number
LCMXO256C-5TN100C
Description
MACHXO PLD FLASH, SCRAM 1.8V, 256
Manufacturer
LATTICE SEMICONDUCTOR
Series
MachXOr
Datasheet
1.LCMXO1200C-5TN144C.pdf
(244 pages)
Specifications of LCMXO256C-5TN100C
Cpld Type
FLASH
No. Of Macrocells
128
No. Of I/o's
78
Propagation Delay
3.5ns
Global Clock Setup Time
1.3ns
Frequency
600MHz
Supply Voltage Range
1.71V To 3.465V
Operating
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256C-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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PCLK PIO (Primary Clock Pads)
There are two PCLK PIOs on top and two PIOs on bottom, for a total of four pins for each MachXO device. These
pads connect directly to the global clock network.
PLL PIO
There are two pad pairs (one pad pair on the upper side and one pair on the lower side) for the MachXO2280 and
one pad pair for the MachXO1200.
PLLFB PIO
Two pad pairs (one pad pair on the upper side and one pair on the lower side) for the MachXO2280 and one pad
pair for the MachXO1200.
Primary Clock Mux Connectivity
The Primary Clock Mux input sources include:
• Primary clock input pins.
• PLL outputs
• From routing
The Primary Clock Mux outputs feed four clock input switch boxes in a PFU.
Figure 10-10. Primary Clock Net
Global Clocks
Global Clocks
From Routing
From Routing
Outputs
PLL
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
12
4
4
6
6
MachXO256 and
MachXO2280
MachXO640
PCLK0
PCLK1
PCLK2
PCLK3
PCLK0
PCLK1
PCLK2
PCLK3
10-14
Global Clocks
From Routing
Outputs
PLL
CLKOP
CLKOS
CLKOK
4
9
3
Design and Usage Guide
MachXO sysCLOCK PLL
MachXO1200
PCLK0
PCLK1
PCLK2
PCLK3
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