LCMXO256C-5TN100C LATTICE SEMICONDUCTOR, LCMXO256C-5TN100C Datasheet - Page 169
![MACHXO PLD FLASH, SCRAM 1.8V, 256](/photos/19/0/190054/42334689_sml.jpg)
LCMXO256C-5TN100C
Manufacturer Part Number
LCMXO256C-5TN100C
Description
MACHXO PLD FLASH, SCRAM 1.8V, 256
Manufacturer
LATTICE SEMICONDUCTOR
Series
MachXOr
Datasheet
1.LCMXO1200C-5TN144C.pdf
(244 pages)
Specifications of LCMXO256C-5TN100C
Cpld Type
FLASH
No. Of Macrocells
128
No. Of I/o's
78
Propagation Delay
3.5ns
Global Clock Setup Time
1.3ns
Frequency
600MHz
Supply Voltage Range
1.71V To 3.465V
Operating
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256C-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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MachXO sysCLOCK PLL
Lattice Semiconductor
Design and Usage Guide
Figure 10-5. Pre-Map Preference Editor
Dynamic Delay Adjustment
The Dynamic Delay Adjustment is controlled by the DDAMODE input. When the DDAMODE input is set to “1”, the
delay control is done through the inputs, DDAIZR, DDAILAG and DDAIDEL(2:0). For this mode, the attribute
“DELAY_CNTL” must be set to “DYNAMIC”. Table 10-4 shows the delay adjustment values based on the attri-
bute/input settings.
In this mode, the PLL may come out of lock due to the abrupt change of phase. RST must be asserted to re-lock
the PLL. Upon de-assertion of RST, the PLL will start the lock-in process and will take the t
time to complete
LOCK
the PLL lock.
10-7
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