EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 5

• Manufacturer Part Number: EPM7160SQC160-10N
• Description: IC PLD EEPROM 160 MACROCELL 10NS QFP-160
• Manufacturer: Altera
• Series: MAX 7000Sr

Specifications of EPM7160SQC160-10N

• Cpld Type: EEPROM
• No. Of Macrocells: 160
• No. Of I/o's: 104
• Propagation Delay: 10ns
• Global Clock Setup Time: 3.4ns
• Frequency: 149.3MHz
• Supply Voltage Range: 4.75V To 5.25V
• Family Name: MAX 7000S
• Memory Type: EEPROM
• # Macrocells: 160
• Number Of Usable Gates: 3200
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 10
• # I/os (max): 104
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
(1)
(2)
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Table 5. MAX 7000 Maximum User I/O Pins
Device
When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
Perform a complete thermal analysis before committing a design to this device package. For more information, see
the
Operating Requirements for Altera Devices Data
PLCC
44-
Pin
36
36
36
36
PQFP
44-
Pin
36
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
TQFP
44-
Pin
36
36
36
36
PLCC
68-
Pin
52
52
PLCC
84-
Pin
68
68
64
68
68
64
64
MAX 7000 Programmable Logic Device Family Data Sheet
Note (1)
Sheet.
PQFP
100-
Pin
68
76
84
84
84
68
84
84
TQFP
100-
Pin
(2)
(2)
Table
100
100
104
104
124
124
132
PQFP
160-
Pin
5.
(2)
160-
PGA
124
Pin
192-
PGA
164
Pin
164
PQFP
208-
Pin
(2)
RQFP
208-
164
164
Pin
5