EPM7160SQC160-10N Altera, EPM7160SQC160-10N Datasheet - Page 49

IC PLD EEPROM 160 MACROCELL 10NS QFP-160

EPM7160SQC160-10N

Manufacturer Part Number
EPM7160SQC160-10N
Description
IC PLD EEPROM 160 MACROCELL 10NS QFP-160
Manufacturer
Altera
Series
MAX 7000Sr
Datasheet

Specifications of EPM7160SQC160-10N

Cpld Type
EEPROM
No. Of Macrocells
160
No. Of I/o's
104
Propagation Delay
10ns
Global Clock Setup Time
3.4ns
Frequency
149.3MHz
Supply Voltage Range
4.75V To 5.25V
Family Name
MAX 7000S
Memory Type
EEPROM
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
104
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7160SQC160-10N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7160SQC160-10N
Manufacturer:
ALTERA
0
Altera Corporation
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t
t
t
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t
t
t
t
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t
t
t
t
t
t
Symbol
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 35. EPM7192S External Timing Parameters (Part 2 of 2)
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2)
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
C1 = 35 pF
(2)
C1 = 35 pF
(4)
(4)
(5)
Conditions
Conditions
(6)
(6)
(3)
MAX 7000 Programmable Logic Device Family Data Sheet
125.0
125.0
166.7
Min
1.8
3.0
3.0
3.0
1.0
Min
1.1
-7
-7
Max
7.8
8.0
8.0
Max
Note (1)
Note (1)
0.3
0.3
3.2
4.2
1.2
3.1
3.1
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
Speed Grade
100.0
100.0
125.0
Min
3.0
4.0
4.0
4.0
1.0
Speed Grade
Min
2.0
-10
-10
Max
10.0
10.0
10.0
Max
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
100.0
Min
76.9
76.9
4.0
6.0
6.0
6.0
1.0
Min
4.0
-15
-15
Max
13.0
15.0
13.0
Max
10.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
7.0
6.0
7.0
6.0
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49

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