LFE2-12E-6QN208C LATTICE SEMICONDUCTOR, LFE2-12E-6QN208C Datasheet - Page 5

• Manufacturer Part Number: LFE2-12E-6QN208C
• Description: IC, LATTICEECP2 FPGA, 420MHZ, QFP-208
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2r

Specifications of LFE2-12E-6QN208C

• No. Of Logic Blocks: 12000
• No. Of Macrocells: 6000
• No. Of Speed Grades: 6
• No. Of I/o's: 131
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 221Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
Programmable
Function Units
(PFUs)
sysDSP Blocks
Multiply and
Accumulate Support
sysMEM Block RAM
18kbit Dual Port
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Programmable
Function Units
(PFUs)
DSP Blocks
Multiply & Accumulate
Support
sysMEM Block
RAM 18kbit Dual Port
On-Chip
Oscillator
2-2
Channel
3
Channel
2
LatticeECP2/M Family Data Sheet
Channel
1
Channel
0
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
SERDES
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysCLOCK SPLLs
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
Architecture