LFXP2-40E-5FN672C LATTICE SEMICONDUCTOR, LFXP2-40E-5FN672C Datasheet - Page 44

IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-672

LFXP2-40E-5FN672C

Manufacturer Part Number
LFXP2-40E-5FN672C
Description
IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-672
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet

Specifications of LFXP2-40E-5FN672C

No. Of Logic Blocks
40000
No. Of Macrocells
20000
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
540
Clock Management
PLL
Total Ram Bits
885Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Density Shifting
The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack-
age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-
lization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
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