LFXP2-40E-5FN672C LATTICE SEMICONDUCTOR, LFXP2-40E-5FN672C Datasheet - Page 32
![IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-672](/photos/19/3/190399/4582502_sml.jpg)
LFXP2-40E-5FN672C
Manufacturer Part Number
LFXP2-40E-5FN672C
Description
IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-672
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-40E-5FN672C
No. Of Logic Blocks
40000
No. Of Macrocells
20000
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
540
Clock Management
PLL
Total Ram Bits
885Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High
Speed I/O Interface.
Figure 2-27. Output and Tristate Block
DQSXFER
DQSXFER
ONEG1
OPOS1
ONEG0
OPOS0
ONEG1
OPOS1
ONEG0
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-29
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
Q
Q
Q
Q
Q
Q
Q
Q
Comp PIO (B) in LVDS I/O Pair
LatticeXP2 Family Data Sheet
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
0
1
0
1
Architecture
DO
DO
TO
TO
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