EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 346
EP3C10M164C8N
Manufacturer Part Number
EP3C10M164C8N
Description
IC CYCLONE III FPGA 402MHZ BGA-164
Manufacturer
Altera
Series
Cyclone IIIr
Specifications of EP3C10M164C8N
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
106
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
106
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2–28
Table 2–39. Glossary (Part 3 of 5)
Cyclone III Device Handbook, Volume 2
Letter
S
T
Single-ended
Voltage
referenced I/O
Standard
SW (Sampling
Window)
t
TCCS (Channel-
to-channel-skew)
tcin
t
tcout
t
t
t
Timing Unit
Interval (TUI)
t
t
t
tpllcin
tpllcout
C
C O
DUTY
FA LL
H
INJITTER
OUTJITTER_DEDC LK
OUTJITTER_IO
Term
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■
■
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
High-speed receiver and transmitter input and output clock period.
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80 to 20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Delay from the clock pad to the I/O output register.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
V
V
OH
OL
C O
variation and clock skew. The clock is included in the TCCS measurement.
V
Definitions
REF
Chapter 2: Cyclone III LS Device Data Sheet
© December 2009 Altera Corporation
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
SS
C
/w).
Glossary
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