STA339BWS13TR STMicroelectronics, STA339BWS13TR Datasheet - Page 3

• Manufacturer Part Number: STA339BWS13TR
• Description: DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
• Manufacturer: STMicroelectronics

Specifications of STA339BWS13TR

• Svhc: No SVHC (15-Dec-2010)
• No. Of Pins: 36
• Operating Temperature Range: -20°C To +70°C
• Supply Voltage Max: 21.5V
• Supply Voltage Min: 4.5V
• Termination: RoHS Compliant
• Package / Case: PowerSSO
• Interface: I2C
• Interface Type: I2C
• Rohs Compliant: Yes

STA339BWS
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 42
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 45
6.3.1
6.3.2
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 47
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 49
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 55
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 43
Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . 44
Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . 49
Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 49
Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 50
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 54
Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 55
Limiter 2 extended attack threshold (addr 0x34) . . . . . . . . . . . . . . . . . . 55
Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 55
Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 55
Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 55
Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 56
Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 56
Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 56
Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 57
Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 57
Doc ID 15276 Rev 3
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