DSPIC33FJ128MC804-E/ML Microchip Technology, DSPIC33FJ128MC804-E/ML Datasheet - Page 268

• Manufacturer Part Number: DSPIC33FJ128MC804-E/ML
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128MC804-E/ML

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 35
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 21-26: CiTRmnCON: ECAN™ Tx/Rx BUFFER m CONTROL REGISTER
DS70291D-page 268
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note:
Note 1: This bit is cleared when TXREQ is set.
TXENm
TXENn
R/W-0
R/W-0
The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
TXABTm: Message Aborted bit
1 = Message was aborted
0 = Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
1 = Requests that a message be sent. The bit automatically clears when the message is successfully
0 = Clearing the bit to ‘0’ while set requests a message abort
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
TXABTm
TXABTn
sent
R-0
R-0
(m = 0,2,4,6; n = 1,3,5,7)
(1)
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
TXLARBm
TXLARBn
R-0
R-0
(1)
TXERRm
TXERRn
(1)
R-0
R-0
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQm
TXREQn
R/W-0
R/W-0
(1)
RTRENm
RTRENn
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
TXmPRI<1:0>
TXnPRI<1:0>
R/W-0
R/W-0
bit 8
bit 0