DSPIC33FJ128MC804-E/ML Microchip Technology, DSPIC33FJ128MC804-E/ML Datasheet - Page 225

IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44

DSPIC33FJ128MC804-E/ML

Manufacturer Part Number
DSPIC33FJ128MC804-E/ML
Description
IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44
Manufacturer
Microchip Technology
Series
DsPIC33Fr

Specifications of DSPIC33FJ128MC804-E/ML

Core Frequency
40MHz
Core Supply Voltage
3.6V
No. Of I/o's
35
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
REGISTER 17-1:
© 2009 Microchip Technology Inc.
bit 5
bit 4-3
bit 2
bit 1
bit 0
Note 1: CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
2: Read-only bit when QEIM<2:0> = ‘1XX’. Read/write bit when QEIM<2:0> = ‘001’.
3: Prescaler utilized for 16-bit Timer mode only.
4: This bit applies only when QEIM<2:0> = 100 or 110.
5: When configured for QEI mode, this control bit is a ‘don’t care’.
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
TQCKPS<1:0>: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
POSRES: Position Counter Reset Enable bit
1 = Index Pulse resets Position Counter
0 = Index Pulse does not reset Position Counter
TQCS: Timer Clock Source Select bit
1 = External clock from pin QEAx (on the rising edge)
0 = Internal clock (T
UPDN_SRC: Position Counter Direction Selection Control bit
1 = QEBx pin state defines position counter direction
0 = Control/Status bit, UPDN (QEIxCON<11>), defines timer counter (POSxCNT) direction
QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED)
CY
)
Preliminary
(4)
(3)
(5)
DS70291D-page 225

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