DS90CR483VJD National Semiconductor, DS90CR483VJD Datasheet
DS90CR483VJD
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DS90CR483VJD Summary of contents
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... MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable Generalized Block Diagrams © 2004 National Semiconductor Corporation pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. Op- tional DC balancing on a cycle-to-cycle basis, is also pro- vided to reduce ISI (Inter-Symbol Interference) ...
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... Generalized Transmitter Block Diagram Generalized Receiver Block Diagram Ordering Information Order Number DS90CR483VJD DS90CR484VJD www.national.com Function Transmitter (Serializer) Receiver (Deserializer) 2 10091802 10091803 Package VJD100A VJD100A ...
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... V Input Clamp Voltage CL I Input Current IN I Output Short Circuit OS Current (Note 1) DS90CR484VJD Package Derating: DS90CR483VJD DS90CR484VJD −0.3V to +4V ESD Rating: −0.3V to +5.5V DS90CR483 (HBM, 1.5kΩ, 100pF) + 0.3V) (EIAJ, 0Ω, 200pF) CC DS90CR484 −0.3V to +3.6V (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) − ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVDS DRIVER DC SPECIFICATIONS |V | Differential Output OD Voltage ∆V Change between Complimentary Output States V Offset Voltage OS ∆V Change ...
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Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LLHT LVDS Low-to-High Transition Time, (Figure 2), PRE = 0.75V (disabled) LVDS Low-to-High Transition Time, (Figure 2), PRE = Vcc (max) LHLT LVDS High-to-Low Transition ...
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Chipset RSKM Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 7). See Applications Infor- mation section for more details on this parameter and how to apply it. Symbol Parameter RSKM Receiver Skew Margin without Deskew in ...
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AC Timing Diagrams Note 9: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. FIGURE 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times FIGURE 3. DS90CR484 (Receiver) CMOS/TTL Output Load and ...
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AC Timing Diagrams FIGURE 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times FIGURE 6. DS90CR484 (Receiver) Setup/Hold and High/Low Times FIGURE 7. DS90CR483 (Transmitter) Propagation Delay - Latency www.national.com (Continued) 8 10091815 10091816 10091827 ...
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AC Timing Diagrams (Continued) FIGURE 8. DS90CR484 (Receiver) Propagation Delay - Latency FIGURE 9. DS90CR483 (Transmitter) Phase Lock Loop Set Time 10091828 10091819 9 www.national.com ...
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AC Timing Diagrams FIGURE 10. DS90CR484 (Receiver) Phase Lock Loop Set Time FIGURE 11. DS90CR483 (Transmitter) Power Down Delay FIGURE 12. DS90CR484 (Receiver) Power Down Delay www.national.com (Continued) 10 10091820 10091821 10091822 ...
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AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max TPPOS — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + ...
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LVDS Interface Optional features supported: Pre-emphasis, and Deskew FIGURE 15. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Enabled www.national.com 12 10091804 ...
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LVDS Interface (Continued) Optional feature supported: Pre-emphasis FIGURE 16. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Disabled 13 10091805 www.national.com ...
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Applications Information The DS90CR483/DS90CR484 chipset is improved over prior generations of Channel Link devices and offers higher band- width support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum clock rate is increased to 112 ...
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Applications Information DC Balance mode is set when the BAL pin on the transmitter is tied HIGH - see pin descriptions. DC Balancing is useful on long cable applications which are typically greater than 5 meters in length. 3. Deskew: ...
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Applications Information generations of Channel Link devices and offers higher band- width support and longer cable drive with the use of DC balanced data transmission, pre-emphasis. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output ...
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... Typical Data Rate vs Cable Length Curve DATA RATE VS CABLE LENGTH TEST PROCEDURE The Data Rate vs Cable Length graph was generated using National Semiconductor’s CLINK3V48BT-112 Evaluation Kit and 3M’s Mini D Ribbon (MDR) Cable under typical conditions (Vcc = 3.3V, Temp = +25˚C). A Tektronix MB100 Bit-Error-Rate Tester ...
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DS90CR483 Pin Description—Channel Link Transmitter Pin Name I/O TxIN I TxOUTP O TxOUTM O TxCLKIN I TxCLKP O TxCLKM PLLSEL I PRE I DS_OPT I BAL GND I PLLV I CC PLLGND I ...
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DS90CR484 Pin Description—Channel Link Receiver Pin Name I/O RxINP I RxINM I RxOUT O RxCLKP I RxCLKM I RxCLKOUT O PLLSEL I DESKEW GND I PLLV I CC PLLGND I LVDSV I CC LVDSGND ...
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Pin Diagram www.national.com Transmitter - DS90CR483 - TQFP (TOP VIEW) 20 10091806 ...
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Pin Diagram Receiver - DS90CR484 - TQFP (TOP VIEW) 21 10091807 www.national.com ...
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... Physical Dimensions Order Number DS90CR483VJD and DS90CR484VJD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or ...