DS90CR286MTD National Semiconductor, DS90CR286MTD Datasheet - Page 6

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DS90CR286MTD

Manufacturer Part Number
DS90CR286MTD
Description
IC, LVDS RECEIVER, TSSOP-56
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90CR286MTD

Supply Current
105mA
Supply Voltage Range
3V To 3.6V
Driver Case Style
TSSOP
No. Of Pins
56
Operating Temperature Range
-40°C To +85°C
Device Type
Differential Receiver
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
No
Data Rate Max
462Mbps
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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RSRC
RHRC
RCCD
RPLLS
RPDD
Receiver Switching Characteristics
Symbol
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and clock jitter less than 250 ps).
Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
AC Timing Diagrams
RxOUT Setup to RxCLK OUT (Figure 7)
RxOUT Hold to RxCLK OUT (Figure 7)
RxCLK IN to RxCLK OUT Delay (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 15)
FIGURE 2. DS90CR285 (Transmitter) LVDS Output Load and Transition Times
FIGURE 1. “Worst Case” Test Pattern
Parameter
(Continued)
6
01291003
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
01291004
Min
6.5
2.5
6.0
2.5
4.0
5.0
14.0
Typ
8.0
8.0
4.0
6.7
6.6
01291002
Max
8.0
9.0
10
1
Units
ms
ns
ns
ns
ns
ns
ns
µs

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