DS90CR286MTD National Semiconductor, DS90CR286MTD Datasheet

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DS90CR286MTD

Manufacturer Part Number
DS90CR286MTD
Description
IC, LVDS RECEIVER, TSSOP-56
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90CR286MTD

Supply Current
105mA
Supply Voltage Range
3V To 3.6V
Driver Case Style
TSSOP
No. Of Pins
56
Operating Temperature Range
-40°C To +85°C
Device Type
Differential Receiver
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
No
Data Rate Max
462Mbps
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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© 2004 National Semiconductor Corporation
DS90CR285/DS90CR286
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-66 MHz
General Description
The DS90CR285 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR286 receiver con-
verts the LVDS data streams back into 28 bits of LVCMOS/
LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits
of TTL data are transmitted at a rate of 462 Mbps per LVDS
data channel. Using a 66 MHz clock, the data throughput is
1.848 Gbit/s (231 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data and one clock, up to 58 conductors are required. With
the Channel Link chipset as few as 11 conductors (4 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
See NS Package Number MTD56
Order Number DS90CR285MTD
DS90CR285
DS012910
01291001
The 28 LVCMOS/LVTTL inputs can support a variety of
signal combinations. For example, seven 4-bit nibbles or
three 9-bit (byte + parity) and 1 control.
Features
n Single +3.3V supply
n Chipset (Tx + Rx) power consumption
n Power-down mode (
n Up to 231 Megabytes/sec bandwidth
n Up to 1.848 Gbps data throughput
n Narrow bus reduces cable size
n 290 mV swing LVDS devices for low EMI
n +1V common mode range (around +1.2V)
n PLL requires no external components
n Both devices are offered in a Low profile 56-lead
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n ESD Rating
n Operating Temperature: −40˚C to +85˚C
TSSOP package
See NS Package Number MTD56
Order Number DS90CR286MTD
>
7 kV
<
DS90CR286
0.5 mW total)
<
250 mW (typ)
www.national.com
July 2004
01291027

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DS90CR286MTD Summary of contents

Page 1

... Both devices are offered in a Low profile 56-lead TSSOP package n Rising edge data strobe n Compatible with TIA/EIA-644 LVDS standard > n ESD Rating n Operating Temperature: −40˚C to +85˚C 01291001 Order Number DS90CR286MTD See NS Package Number MTD56 DS012910 July 2004 < 250 mW (typ) < 0.5 mW total) ...

Page 2

Pin Diagrams for TSSOP Packages DS90CR285 Typical Application www.national.com 01291021 2 DS90CR286 01291022 01291023 ...

Page 3

... TH V Differential Input Low Threshold TL I Input Current IN (Note 1) Maximum Package Power Dissipation DS90CR285MTD DS90CR286MTD Package Derating: −0.3V to +4V DS90CR285MTD + 0.3V) DS90CR286MTD CC + 0.3V) ESD Rating CC (HBM, 1.5 kΩ, 100 pF) + 0.3V) CC Recommended Operating + 0.3V) CC Conditions Continuous +150˚C Supply Voltage (V −65˚C to +150˚C ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current Worst CCTW Case (with Loads) I Transmitter Supply Current Power CCTZ Down RECEIVER SUPPLY CURRENT I Receiver Supply Current ...

Page 5

Transmitter Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol Parameter TPPos3 Transmitter Output Pulse Position for Bit3 TPPos4 Transmitter Output Pulse Position for Bit4 TPPos5 Transmitter Output Pulse Position for Bit5 TPPos6 Transmitter ...

Page 6

Receiver Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol RSRC RxOUT Setup to RxCLK OUT (Figure 7) RHRC RxOUT Hold to RxCLK OUT (Figure 7) RCCD RxCLK IN to RxCLK OUT Delay (Figure ...

Page 7

AC Timing Diagrams (Continued) FIGURE 3. DS90CR286 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR285 (Transmitter) Input Clock Transition Time Note 8: Measurements DIFF Note 9: TCCS measured between earliest and latest LVDS edges. ...

Page 8

AC Timing Diagrams FIGURE 6. DS90CR285 (Transmitter) Setup/Hold and High/Low Times FIGURE 7. DS90CR286 (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90CR285 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR286 (Receiver) Clock In to Clock Out Delay www.national.com ...

Page 9

AC Timing Diagrams (Continued) FIGURE 10. DS90CR285 (Transmitter) Phase Lock Loop Set Time FIGURE 11. DS90CR286 (Receiver) Phase Lock Loop Set Time FIGURE 12. Seven Bits of LVDS in Once Clock Cycle 01291014 01291015 9 01291013 www.national.com ...

Page 10

AC Timing Diagrams FIGURE 13. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs www.national.com (Continued) FIGURE 14. Transmitter Powerdown DeIay FIGURE 15. Receiver Powerdown Delay 10 01291016 01291017 01291018 ...

Page 11

AC Timing Diagrams (Continued) FIGURE 16. Transmitter LVDS Output Pulse Position Measurement 11 01291019 www.national.com ...

Page 12

AC Timing Diagrams www.national.com (Continued) FIGURE 17. Receiver LVDS Input Strobe Position 12 01291028 ...

Page 13

AC Timing Diagrams C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + Source ...

Page 14

DS90CR286 MTD56 (TSSOP) Package Pin Description — Channel Link Receiver (Continued) Pin Name I/O No. PLL GND I 2 Ground pin for PLL. LVDS Power supply pin for LVDS inputs. CC LVDS GND I 3 Ground pins ...

Page 15

Applications Information number of bypass capacitors, the PLL V FIGURE 20. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit ...

Page 16

Applications Information FIGURE 21. Single-Ended and Differential Waveforms www.national.com (Continued) 16 01291026 ...

Page 17

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) Order Number DS90CR285MTD or DS90CR286MTD NS Package Number MTD56 2. A critical component is any component of a life ...

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