DP83848HSQ National Semiconductor, DP83848HSQ Datasheet - Page 35

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DP83848HSQ

Manufacturer Part Number
DP83848HSQ
Description
IC, TRANSCEIVER, ENET PHYTER, 40LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83848HSQ

Data Rate
100Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
92mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +125°C
Digital Ic Case Style
LLP
No. Of
RoHS Compliant
Interface Type
MII Serial, RMII
Rohs Compliant
Yes

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5.4 Power Feedback Circuit
To ensure correct operation for the DP83848H, parallel
caps with values of 10 F (Tantalum) and 0.1 F should
be placed close to pin 19 (PFBOUT) of the device.
Pin 16 (PFBIN1) and pin 30 (PFBIN2) must be connected
to pin 19 (PFBOUT), each pin requires a small capacitor
(0.1 F). See Figure 13 below for proper connections.
5.5 Power Down
The device can be put in a Power Down mode by setting
bit 11 (Power Down) in the Basic Mode Control Register,
BMCR (0x00h).
5.6 Energy Detect Mode
When Energy Detect is enabled and there is no activity on
the cable, the DP83848H will remain in a low power mode
while monitoring the transmission line. Activity on the line
will cause the DP83848H to go through a normal power
up sequence. Regardless of cable activity, the DP83848H
will occasionally wake up the transmitter to put ED pulses
on the line, but will otherwise draw as little power as possi-
ble. Energy detect functionality is controlled via register
Energy Detect Control (EDCR), address 0x1Dh.
Pin 30 (PFBIN2)
Pin 19 (PFBOUT)
Pin 16 (PFBIN1)
Figure 13. Power Feeback Connection
0.1 F
0.1 F
10 F
+
-
0.1 F
35
6.0 Reset Operation
The DP83848H includes an internal power-on reset
(POR) function and does not need to be explicitly reset for
normal operation after power up. If required during normal
operation, the device can be reset by a hardware or soft-
ware reset.
6.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1
RESET_N. This will reset the device such that all registers
will be reinitialized to default values and the hardware
configuration values will be re-latched into the device
(similar to the power-up/reset operation).
6.2 Software Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is
approximately 1 s.
The software reset will reset the device such that all regis-
ters will be reset to default values and the hardware con-
figuration values will be maintained. Software driver code
must wait 3 s following a software reset before allowing
further serial MII operations with the DP83848H.
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