DP83848HSQ National Semiconductor, DP83848HSQ Datasheet - Page 11

• Manufacturer Part Number: DP83848HSQ
• Description: IC, TRANSCEIVER, ENET PHYTER, 40LLP
• Manufacturer: National Semiconductor

Specifications of DP83848HSQ

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Digital Ic Case Style: LLP
• No. Of: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes

1.4 LED Interface
See Table 3 for LED Mode Selection.
1.5 Reset
1.6 Strap Options
DP83848H uses many functional pins as strap options.
The values of these pins are sampled during reset and
used to strap the device into specific modes of operation.
The strap option pin assignments are defined below. The
functional pin name is indicated in parentheses.
25MHz_OUT
LED_LINK
RESET_N
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
Signal Name
Signal Name
Signal Name
Signal Name
S, O, PU
S, O, PU
S, O, PD
Type
Type
Type
Type
I, PU
O
Pin #
Pin #
Pin #
Pin #
21
22
23
35
36
37
38
39
25 MHz CLOCK OUTPUT:
This pin provides a 25 MHz clock output to the system. This al-
lows other devices to use the reference clock from the DP83848H
without requiring additional clock sources.
RMII Mode: This pin provides a 50 MHz clock output to the sys-
tem. For RMII mode, it is not recommended that the system clock
out be used as the reference clock to the MAC without first verify-
ing the interface timing. See AN-1405 for more details.
LINK LED: In Mode 1, this pin indicates the status of the LINK.
The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2, this pin indicates transmit and receive
activity in addition to the status of the Link. The LED will be ON
when Link is good. It will blink when the transmitter or receiver is
active.
RESET: Active Low input that initializes or re-initializes the
DP83848H. Asserting this pin low for at least 1 s will force a reset
process to occur. All internal registers will re-initialize to their de-
fault states as specified for each bit in the Register Block section.
All strap options are re-initialized as well.
PHY ADDRESS [4:0]: The DP83848H provides five PHY ad-
dress pins, the state of which are latched into the PHYCTRL reg-
ister at system Hardware-Reset.
The DP83848H supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mode must be se-
lected by strapping Phy Address 0; changing to Address 0 by reg-
ister write will not put the Phy in the MII isolate mode. Please refer
to section 2.3 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
11
A 2.2 k resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func-
tions after reset is deasserted, they should not be con-
nected directly to VCC or GND.
Description
Description
Description
Description
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