CS4228A-KSZ Cirrus Logic Inc, CS4228A-KSZ Datasheet - Page 26

IC, AUDIO CODEC, 24BIT, 100KHZ, SSOP-28

CS4228A-KSZ

Manufacturer Part Number
CS4228A-KSZ
Description
IC, AUDIO CODEC, 24BIT, 100KHZ, SSOP-28
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4228A-KSZ

Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
6
No. Of Input Channels
2
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
90dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4228A-KSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Master Clock - MCLK
Serial Control Interface Clock - SCL/CCLK
Serial Control Data I/O - SDA/CDIN
Address Bit 0 / Chip Select - ADO/CS
Reset - RST
26
Sample
(kHz)
Rate
44.1
88.2
32
48
64
96
Pin 10, Input
Function:
Pin 11, Input
Function:
Pin 12, Bidirectional/Input
Function:
Pin 13, Input
Function:
Pin 14, Input
Function:
The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate
Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate in High Rate Mode (HRM). Table
2 illustrates several standard audio sample rates and the required master clock frequencies. The
MCLK/Fs ration is set by the CI1:0 bits in the CODEC Clock Mode register
Clocks serial control data into or out of SDA/CDIN.
In I
open drain output operation. In SPI mode, CDIN is the control port data input line. The state of the SDOUT
pin during reset is used to set the control port mode.
In I
interface.
When low, the device enters a low power mode and all internal registers are reset to the default settings,
including the control port. The control port can not be accessed when reset is low.
When high, the control port and the CODEC become operational.
2
2
C mode, AD0 is the LSB of the chip address. In SPI mode, CS is used as a enable for the control port
C mode, SDA is a bidirectional control port data line. A pull up resistor must be provided for proper
4.0960
5.6448
6.1440
64x
-
-
-
12.2880
11.2896
8.1920
128x
-
-
-
Table 2. Common Master Clock Frequencies
HRM
12.2880
16.9344
18.4320
192x
-
-
-
16.3840
22.5792
24.5760
256x
MCLK (MHz)
-
-
-
4.0960
5.6448
6.1440
128x
-
-
-
12.2880
11.2896
8.1920
256x
-
-
-
BRM
12.2880
16.9344
18.4320
384x
-
-
-
CS4228
DS307PP1
16.3840
22.5792
24.5760
512x
-
-
-

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