CS4228A-KSZ Cirrus Logic Inc, CS4228A-KSZ Datasheet - Page 17

• Manufacturer Part Number: CS4228A-KSZ
• Description: IC, AUDIO CODEC, 24BIT, 100KHZ, SSOP-28
• Manufacturer: Cirrus Logic Inc

Specifications of CS4228A-KSZ

• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 6
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 90dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAP allows successive reads or writes of consecu-
tive registers. Each byte is separated by an ac-
knowledge bit.
Control Port Bit Definitions
All registers are read/write, except the Chip Status
register which is read-only. For more detailed in-
formation, see the bit definition tables starting on
page 19.
Power-up/Reset/Power Down Mode
Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
DS307PP1
CCLK
CS
CDIN
SCL
SDA
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
ADDRESS
MAP = Memory Address Pointer
0010000
CHIP
Start
001000
R/W
Figure 14. Control Port Timing, I
Figure 13. Control Port Timing, SPI mode
MAP
AD 0
MSB
byte 1
R/W
DATA
ACK
byte n
LSB
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re-
set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.
The CS4228 will enter a stand-by mode if the mas-
ter clock source stops for approximately 10 s or if
the number of MCLK cycles per LRCK period var-
ies by more than 32. Should this occur, the control
registers retain their settings.
D7:0
ADDRESS
CHIP
0010000
Note 1
ACK
2
C Mode
R/W
D7:0
ACK
Stop
CS4228
17