LIS202DLTR STMicroelectronics, LIS202DLTR Datasheet

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... Table 1. Device summary Order code LIS202DL LIS202DLTR December 2007 The LIS202DL has dynamically user selectable full scales of ±2g/±8g and it is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz. A self-test capability allows the user to check the functioning of the sensor in the final application ...

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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block ...

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LIS202DL 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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LIS202DL List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram SELF TEST REFERENCE 1.2 Pin description Figure 2. Pin connection Y 6 6/36 CHARGE AMPLIFIER A/D MUX ...

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LIS202DL Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins GND 0V supply Reserved Connect to Vdd GND 0V supply GND 0V supply ...

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Mechanical and electrical specifications 2 Mechanical and electrical specifications 2.1 Mechanical characteristics (All the parameters are specified @ Vdd=2 25°C unless otherwise noted) Table 3. Mechanical characteristics Symbol Parameter (3) FS Measurement range So Sensitivity Sensitivity change ...

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LIS202DL 2.2 Electrical characteristics (All the parameters are specified @ Vdd=2.5V, T= 25°C unless otherwise noted) Table 4. Electrical characteristics Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins Supply voltage Idd Supply current Current consumption in IddPdn power-down mode Digital ...

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Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - Serial Peripheral Interface Subject to general operating conditions for Vdd and top. Table 5. SPI Slave Timing Values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS ...

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LIS202DL 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table Slave Timing Values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) ...

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Mechanical and electrical specifications 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not ...

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LIS202DL 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of ...

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Functionality 3 Functionality The LIS202DL is an ultracompact, low-power, digital output 2-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...

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LIS202DL 4 Application hints Figure 5. LIS202DL electrical connection Vdd 10uF 100nF GND Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied ...

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Digital interfaces 5 Digital interfaces The registers embedded inside the LIS202DL may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are ...

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LIS202DL 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. ...

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Digital interfaces Table 13. Transfer when master is receiving (reading) one byte of data from slave: Master Slave Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave: Master Slave Master Slave Data are transmitted in ...

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LIS202DL CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is ...

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Digital interfaces bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 8. Multiple bytes SPI read protocol (2 ...

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LIS202DL Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial ...

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Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 15. Register address map Name Reserved (do not modify) Who_Am_I Reserved (do not modify) ...

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LIS202DL 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...

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Register description STP, STM bits are used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to thus allowing to check the functionality of the whole ...

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LIS202DL Table 21. Truth table (21h) HPcoeff2 7.4 CTRL_REG3 [Interrupt CTRL register] (22h) Table 22. Register (22h) IHL PP_OD Table 23. Register description (22h) IHL Interrupt active high, low. Default value 0. (0: active high; 1: ...

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Register description 7.5 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all two axes are instantaneously set to 0g. This allows to overcome the ...

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LIS202DL 7.9 WU_CFG_1 (30h) Table 29. Register (30h) AOI LIR Table 30. Register description (30h) And/Or combination of Interrupt events. Default value: 0 AOI (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into ...

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Register description Table 32. Register description (31h) X High. Default value (0: no interrupt event has occurred) X Low. Default value (0: no interrupt event has occurred) Wake-up source register. Read only ...

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LIS202DL 7.13 WU_CFG_2 (34h) Table 37. Register (34h) AOI LIR Table 38. Register description (34h) AOI And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) LIR Latch Interrupt request ...

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Register description Wake-up source register. Read only register. Reading at this address clears WU_SRC_2 register and the WU_2 interrupt and allows the refreshment of data in the WU_SRC_2 register if the latched option was chosen. 7.15 WU_THS_2 (36h) Table 41. ...

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LIS202DL 8 Typical performance characteristics 8.1 Mechanical characteristics at 25°C Figure 12. X axis Zero-g level at 2 −150 −100 −50 0 Zero−g Level Offset [mg] Figure 14. Y axis Zero-g level at ...

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Typical performance characteristics 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range Figure 16. X axis Zero-g level change vs. temperature at 2 −3 −2 −1 0 Zero−g level ...

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LIS202DL 8.3 Electro-mechanical characteristics at 25°C Figure 20. Current consumption in normal mode at 2 200 220 240 260 280 300 320 Current consumption [uA] Figure 21. Current consumption in power 30 25 ...

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Package information 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...

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LIS202DL 10 Revision history Table 45. Document revision history Date 11-Jun-2007 13-Dec-2007 Revision 1 Initial release. Inserted new Section 2.3: Communication interface characteristics 2 Content reworked to improve readability. Revision history Changes 35/36 ...

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