MPC8313E-RDBC Freescale Semiconductor, MPC8313E-RDBC Datasheet - Page 27

• Manufacturer Part Number: MPC8313E-RDBC
• Description: BOARD CPU 8313E VER 2.2
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8313E-RDBC

• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPC8313E

the signal LB_POR_CFG_BOOT_ECC_DIS (TSEC1_MDC) during power on reset (REVB and REVC
only. REVAx is a reserved switch (RSVD0)). REV1 represents bit 1 of the revision number. Together with
REV0 (implemented by resistor option; the default is 0), REV[0..1] shows the revision number, which is
01 by default. The values can be read from a buffer on the RDB. BOOT1 selects the boot device on the
RDB. By default, BOOT1 is set, so chip-select 0 (CS0) is connected to the NOR Flash. CS1 is connected
to the NAND Flash memory. If BOOT1 is cleared, CS0 is connected to NAND Flash memory, and CS1 is
connected to NOR Flash memory.
3.12
Eight programmable LEDs give status indication and debug information.
An 8-bit write register on the RDB turns the LEDs on and off. The LEDs are arranged so that the most
significant bit represents LED0 and least significant bit represents LED7; that is, LED[0..7]. A write of
0x00 turns on all LEDs, and 0xFF turns off all LEDs.
4
The eTSEC1 RGMII, ULPI USB, and IEEE 1588 signals are multiplexed on the MPC8313E. The
MPC8313E RDB supports switching among the three interfaces using micro-jumpers (REVA boards) or
resistor options (REVA1 or later boards).
Freescale Semiconductor
Micro-Jumper/Resistor Options for eTSEC1
RDB Programmable LEDs
For IEEE 1588 support, use the same setting as for the eTSEC1 RGMII. In
this case, a 50 MHz clock would be provided for the IEEE 1588 TMR_CLK
pin.
PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
LED4
(Green)
LED0
(Red)
Figure 29. Programmable LEDs
LED1
(Yellow)
LED5
(Green)
NOTE
LED2
(Green)
LED6
(Green)
LED3
(Green)
LED7/LCD_EN
(Green)
Micro-Jumper/Resistor Options for eTSEC1
Figure 29
shows the diagram.
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