AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 67

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.10.4
7.10.4.1
32099F–11/2010
SPI Timing
Master mode
The maximum SPI slave output frequency is given by the following formula:
Where
the SPI master setup time. Please refer to the SPI master datasheet for
maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this
clock.
tics section for the maximum frequency of the pins.
Figure 7-13. SPI Master Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
Figure 7-14. SPI Master Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
SPCK
MISO
MOSI
MISO
MOSI
f
PINMAX
SPIn
is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris-
is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA.
f
SPI2
SPI5
SPCKMAX
=
MIN
SPI0
SPI3
(
f
---------------------------- - f
CLKSPI
9
×
2
SPI1
SPI4
,
PINMAX
AT32UC3L016/32/64
,
------------------------------------
SPIn
+
1
t
SETUP
T
)
SETUP
.
f
CLKSPI
T
SETUP
is the
67
is