AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 100

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.17
10.4.18
32099F–11/2010
ADCIFB
ACIFB
1. Pendetect in sleep modes without CLK_ADCIFB will not wake the system
2. 8-bit mode is not working
3. ADC channels six to eight are non-functional
4. VERSION register reads 0x100
5. Using STARTUPTIME value larger than 0x1F will freeze ADC
6. ADCIFB DMA transfers does not work with divided PBA clock
1. Negative offset
2. Generic clock sources in sleep modes
3. VERSION register reads 0x200
The pendetect will not wake the system from a sleep mode if the clock for the
ADCIFB (CLK_ADCIFB) is turned off.
Fix/Workaround
Use a sleep mode where CLK_ADCIFB is not turned off to wake the part using
pendetect.
Do not use the 8-bit mode of the ADCIFB.
Fix/Workaround
Use the 10-bit mode and shift right by 2 bits.
ADC channels six to eight are non-functional.
Fix/Workaround
None.
The VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register
(ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register
(SR.BUSY) will never be cleared.
Fix/Workaround
Do not write values larger than 0x1F to ACR.STARTUP.
DMA requests from the ADCIFB will not be performed when the PBA clock is slower than
the HSB clock.
Fix/Workaround
None
The static offset of the analog comparator is approximately -50mV.
Fix/Workaround
None.
The ACIFB should not use RC32K or CLK_1K as generic clock source if the chip uses sleep
modes.
Fix/Workaround
None.
The VERSION register reads 0x200 instead of 0x212.
Fix/Workaround
None.
AT32UC3L016/32/64
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