AT32UC3L0-XPLD Atmel, AT32UC3L0-XPLD Datasheet - Page 65

• Manufacturer Part Number: AT32UC3L0-XPLD
• Description: KIT DEV/EVAL FOR AT32UC3L0
• Manufacturer: Atmel

Specifications of AT32UC3L0-XPLD

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.10.3.2
32099F–11/2010
Slave mode
Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
Where
the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for
the maximum frequency of the pins.
to the SPI chapter for a description of this clock.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
Where
on CPOL and NCPHA.
datasheet for
chapter for a description of this clock.
Figure 7-10. USART in SPI Slave Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
Figure 7-11. USART in SPI Slave Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
SPCK
SPCK
MISO
MOSI
MISO
MOSI
SPIn
SPIn
is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA.
CPHA= 0)
is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending
T
VALID
USPI6
USPI9
USPI10
USPI7
.
f
CLKSPI
T
f
f
VALID
SPCKMAX
SPCKMAX
is the maximum frequency of the CLK_SPI. Refer to the SPI
is the SPI slave response time. Please refer to the SPI slave
USPI11
USPI8
=
=
f
CLKSPI
MIN f
MIN
(
(
----------------------------------- -
SPIn
PINMAX
is the maximum frequency of the CLK_SPI. Refer
+
1
t
,
VALID
----------- -
SPIn
1
,
AT32UC3L016/32/64
,
f
---------------------------- -
f
---------------------------- -
CLKSPI
CLKSPI
9
9
×
×
2
2
)
)
f
PINMAX
65
is