C8051F380DK Silicon Laboratories Inc, C8051F380DK Datasheet - Page 24
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C8051F380DK
Manufacturer Part Number
C8051F380DK
Description
DEV KIT FOR C8051F380
Manufacturer
Silicon Laboratories Inc
Datasheet
1.TOOLSTICK381DC.pdf
(43 pages)
Specifications of C8051F380DK
Processor To Be Evaluated
C8051F380
Processor Series
C8051F38x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-2012
24
SMBus/I
Master/Slave byte-wise serial data transfers
(can switch on-the-fly)
Clock signal generation on SCL (Master Mode
only) and SDA data synchronization
Timeout/bus error recognition, as defined by
the SMB0CF configuration register
START/STOP timing, detection, and generation
SMBus peripheral supports both software
address decoding and hardware address
decoding
Bus arbitration
Status information
Supports SCL Low Timeout and Bus Free Timeout detection
Hardware address decoding
•Hardware controls the ACK/NACK of the address
and data bytes
•The SMBus peripheral can support masters
without clock stretching at 400 kHz (for I
•Hardware control means less code, less overhead
and more CPU resources available
2
C Peripheral
2
C)