C8051F380DK Silicon Laboratories Inc, C8051F380DK Datasheet - Page 17
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C8051F380DK
Manufacturer Part Number
C8051F380DK
Description
DEV KIT FOR C8051F380
Manufacturer
Silicon Laboratories Inc
Datasheet
1.TOOLSTICK381DC.pdf
(43 pages)
Specifications of C8051F380DK
Processor To Be Evaluated
C8051F380
Processor Series
C8051F38x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-2012
17
USB0 FIFO Allocation
1024 Bytes of FIFO available to the USB
endpoints allocated in XRAM space
Endpoints 1-3 can be configured as IN,
OUT or split mode with both IN and OUT
endpoints
Each endpoint can be double buffered
FIFO access indirectly addressed
Split mode halves the FIFO size available for
each endpoint
Half the memory is available for each transaction
Max. packet size is halved
•
bytes for each IN transaction
Example, IN endpoint 1 double buffered provides 64
Endpoint FIFOs