NUTINY-SDK-M0516 Nuvoton Technology Corporation of America, NUTINY-SDK-M0516 Datasheet - Page 243

• Manufacturer Part Number: NUTINY-SDK-M0516
• Description: BOARD EVAL NUMICRO M051 SERIES
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r
• Type: MCUr

Specifications of NUTINY-SDK-M0516

• Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: M051™ Series, M052/M054/M058/M0516

NuMicro M051
Example 2 , SPI controller is set as a slave device that are controlled by an off-chip master
device, and supposes the off-chip master device to access the on-chip SPI slave controller
through the SPI interface with the following specifications:
Basically, the specification of the connected off-chip master device should be configured detailed
before the following steps
1)
4) If this SPI master will transmits (writes) one byte data to the off-chip slave device, write the
5) If this SPI master just only receives (reads) one byte data from the off-chip slave device, you
6) Enable the GO_BUSY bit (SPI_CNTRL [0] = 1) to start the data transfer at the SPI interface.
7) Waiting for SPI interrupt occurred (if the Interrupt Enable IE bit is set) or just polling the
8) Read out the received one byte data from RX0 [7:0] (SPI_RX0[7:0]) register.
9) Go to 4) to continue another data transfer or set SSR [0] to 0 to inactivate the off-chip slave
5.
6.
7.
byte data that will be transmitted into the TX0[7:0] (SPI_TX0[7:0]) register.
don’t need to care what data will be transmitted and just write 0xFF into the SPI_TX0[7:0]
register.
GO_BUSY bit till it be cleared to 0 by hardware automatically.
devices.
Write the SPI_SSR register a proper value for the related settings of slave mode
Set the bit length of word transfer as 8 bits in TX_BIT_LEN bit field (SPI_CNTRL[7:3] =
0x08)
Set only one time of word transfer in TX_NUM (SPI_CNTRL[9:8] = 0x0)
Set MSB transfer first in MSB bit (SPI_CNTRL[10] = 0), and don’t care the SP_CYCLE
bit field (SPI_CNTRL[15:12]) due to not burst mode in this case
Data bit is latched on positive edge of serial clock
Data bit is driven on negative edge of serial clock
Data is transferred from LSB first
SPICLK is idle at high state
Only one byte of data to be transmitted/received in a transfer
Slave select signal is high level trigger
™
Series Technical Reference Manual
- 243 -
Publication Release Date: Sept 14, 2010
Revision V1.2