RT8204BGQW Richtek USA Inc, RT8204BGQW Datasheet - Page 18

• Manufacturer Part Number: RT8204BGQW
• Description: IC SYNC BUCK W/LDO CTRLR 16WQFN
• Manufacturer: Richtek USA Inc

Specifications of RT8204BGQW

• Topology: Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 2
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RT8204B
LDO Output Capacitor Selection
Low ESR capacitors such as Sanyo POSCAPs or
Panasonic SP-caps are recommended for bulk
capacitance, and ceramic bypass capacitors are
recommended for decoupling high frequency transients.
LDO Input Capacitor Selection
Low ESR capacitors such as Sanyo POSCAPs or
Panasonic SP-caps are recommended for the input
capacitors to provide better load transient response. If the
LDO input is connected from the output of buck converter
(V
LDO MOSFET Selection
Low threshold N-MOSFETs are required. For the device
to work under all operating conditions, a maximum R
must be met to ensure that the output will not go into
dropout :
Note that R
range at the minimum V
Power consumptions of the N-MOSFETs should be taken
into consideration for the selection of various package
types.
www.richtek.com
18
R
DS(ON)(MAX)
OUT1
), a 0.1μF ceramic capacitor will sufficient.
Figure 8. LDO Output Voltage Setting
DS(ON)
LDRV
=
LFB
V
must be met for operating temperature
IN(MIN)
I
OUT(PEAK)
GS
−
LDO_VIN
condition.
V
OUT(MAX)
R3
R4
LDO_VOUT
Ω
DS(ON)
Layout Considerations
Layout is very important in high frequency switching
converter design. If the Layout is designed improperly,
the PCB could radiate excessive noise and contribute to
the converter instability. Certain points must be considered
before starting a layout for the RT8204B.
Connect an RC low pass filter from VDDP to VDD, 1μF
and 10Ω are recommended. Place the filter capacitor
close to the IC.
Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high-voltage switching node.
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high-voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layers as ground
planes and shield the feedback trace from power traces
and components.
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
Power sections should connect directly to ground planes
using multiple vias as required for current handling
(including the chip power ground connections). Power
components should be placed to minimize loops and
reduce losses.
DS8204B-03 March 2011