RT8204BGQW Richtek USA Inc, RT8204BGQW Datasheet - Page 17

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RT8204BGQW

Manufacturer Part Number
RT8204BGQW
Description
IC SYNC BUCK W/LDO CTRLR 16WQFN
Manufacturer
Richtek USA Inc
Datasheet

Specifications of RT8204BGQW

Topology
Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
Function
Any Function
Number Of Outputs
2
Voltage/current - Output 1
Controller
Voltage/current - Output 2
Controller
W/led Driver
No
W/supervisor
No
W/sequencer
No
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The RT8204B LDO contains a power good output pin
(LPGOOD pin) which is an open drain output that will be
pulled low if the output is below the power good threshold
(typically 90% of the programmed output voltage, or 93%
at the start up). The power good detection is active if the
RT8204B LDO is enabled.
The RT8204B LDO also includes a under voltage protection
circuit that monitors the output voltage. If the output voltage
drops below 50% (typical) of the nominal value, as would
occur during over current or short condition, the RT8204B
LDO will pull the LDRV pin low and latch off. The RT8204B
LDO is latched once the UVP is triggered and can only
be relieved by the VDD or LEN power on reset.
LDO Driver and Stability Design
The drive output (LDRV pin) is sink/source capable. The
sink current is typically 2mA while the source current is
typically 2mA in normal operation.
The drive output is also used for stabilizing the loop of the
system using different type of the output capacitor. The
components listed in the table below should be used.
LDO Output Under Voltage Protection(UVP)
The RT8204B LDO has output under voltage protection
that looks at the output to see if it is :
(a) The LDO output voltage is less than 50% (typical) of
its nominal value and
(b) The V
This provides inherent immunity to under voltage shut down
at start up since V
DS8204B-03 March 2011
Note: test condition is output capacitor 220μF(ESR : 9
to 25mΩ) or 100μF(ESR : 9 to 15mΩ) + MLCC
10μFoutput current is from 0.1A to 5A
LDO Configuration
Voltage
Table 1. LDO Configuration and Compensation
1.25V
Input
1.5V
1.5V
1.8V
DRV
is within 900mV (typical) of its maximum.
Voltage
Output
1.05V
1.05V
1.25V
1.5V
DRV
has a slow rate of rising at this
33nF
33nF
33nF
33nF
C7
Compensator
39pF
47pF
47pF
39pF
C8
100Ω
82Ω
43Ω
30Ω
R11
LDO_VIN
LDO_VIN
moment. If both of these criteria are met, the output will
be shut down by means of the V
immediately.
If the VDDP input is coming prior to the LDO_VIN, it could
accidentally meet the UVP fault protection. To avoid
entering UVP latch off, using enable control (LEN pin) to
turn the system on whenever all power supplies are ready.
Please see the power sequencing example as below
(Figure 7).
LDO Output Voltage Setting
The LFB pin connects directly to the inverting input of the
error amplifier, and the output voltage is set using external
resistor R3 and R4 (Figure 8). The following equation is
for adjusting the output voltage.
where V
V
OUT
VDDP
VTH(UV) = 0.88V
VDDP
LEN
MOSFET Drain Supply Comes Up Before RT8204B Supply
LEN
VTH(UV) = 0.88V
RT8204B Supply Comes Up Before MOSFET Drain Supply
= V
VTH(LEN) = 2V
LFB
LFB
Figure 7. Power Supply Sequencing
VTH(LEN) = 2V
is 0.75V (typ.).
×
1
+ ⎜
R3
R4
VTH(LEN) occurs after VTH(UV) is
reached LEN rising with VDDP shown
VTH(LEN) occurs after VTH(UV)
is reached
DRV
RT8204B
pulled to ground
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